| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-06-02 | ARM: Rename the RevOp base class to something more generic. | Gabe Black | |
| 2010-06-02 | ARM: Add a register, immediate, immediate to register base for [su]bfx. | Gabe Black | |
| 2010-06-02 | ARM: Add a base class to support usada8. | Gabe Black | |
| 2010-06-02 | ARM: Add a base class for the sel instruction. | Gabe Black | |
| 2010-06-02 | ARM: Add a base class for extend and add instructions. | Gabe Black | |
| 2010-06-02 | ARM: Generalize the saturation instruction bases for use in other instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement the saturation instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement base classes for the saturation instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement the unsigned saturating instructions. | Gabe Black | |
| 2010-06-02 | ARM: Add base classes suitable for the REV* instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement the swp and swpb instructions. | Gabe Black | |
| 2010-06-02 | ARM: Define versions of MSR and MRS outside the decoder. | Gabe Black | |
| 2010-06-02 | ARM: Implement signed saturating add and/or subtract instructions. | Gabe Black | |
| 2010-06-02 | ARM: Make sure ldm exception return writes back its base in the right mode. | Gabe Black | |
| This change moves the writeback of load multiple instructions to the beginning of the macroop. That way, the MicroLdrRetUop that changes the mode will necessarily happen later, ensuring the writeback happens in the original mode. The actual value in the base register if it also shows up in the register list is undefined, so it's fine if it gets clobbered by one of the loads. For stores where the base register is the lowest numbered in the register list, the original value should be written back. That means stores can't write back at the beginning, but the mode changing problem doesn't affect them so they can continue to write back at the end. | |||
| 2010-06-02 | ARM: Rework how unrecognized/unimplemented instructions are handled. | Gabe Black | |
| Instead of panic immediately when these instructions are executed, an UndefinedInstruction fault is returned. In FS mode (not currently implemented), this is the fault that should, to my knowledge, be triggered in these situations and should be handled using the normal architected mechanisms. In SE mode, the fault causes a panic when it's invoked that gives the same information as the instruction did. When/if support for speculative execution of ARM is supported, this will allow a mispeculated and unrecognized and/or unimplemented instruction from causing a panic. Only once the instruction is going to be committed will the fault be invoked, triggering the panic. | |||
| 2010-06-02 | ARM: Don't rely on undefined behavior to get arithmetic right shift. | Gabe Black | |
| Shifting to the right of a signed value when the MSB is one is technically undefined behavior, even though in my experience it's done the "right thing" and sign extended the value. This replaces the arithmetic right shift code in ARM that uses that coincidence with some code that relies on bit math. | |||
| 2010-06-02 | ARM: Add base classes for VFP load/store multiple. | Gabe Black | |
| 2010-06-02 | ARM: Move the macro mem constructor out of the isa desc. | Gabe Black | |
| This code doesn't use the parser at all, and moving it out reduces the conceptual complexity of that code. | |||
| 2010-06-02 | ARM: Move the inst2string function out of the isa_desc. | Gabe Black | |
| Delete the now empty formats/util.isa. | |||
| 2010-06-02 | ARM: Add base classes for multiply instructions. | Gabe Black | |
| 2010-06-02 | ARM: Eliminate the old style branch instructions. | Gabe Black | |
| 2010-06-02 | ARM: Implement new base classes for branches. | Gabe Black | |
| 2010-06-02 | ARM: Replace the interworking branch base class with a special operand. | Gabe Black | |
| 2010-06-02 | ARM: Fix PC operand handling. | Gabe Black | |
| 2010-06-02 | ARM: Get rid of unnecessary flag calculating functions. | Gabe Black | |
| 2010-06-02 | ARM: Get rid of the unused Jump format. | Gabe Black | |
| 2010-06-02 | ARM: Get rid of obsoleted predicated inst formats, etc. | Gabe Black | |
| 2010-06-02 | ARM: Implement disassembly for the new data processing classes. | Gabe Black | |
| 2010-06-02 | ARM: Move the modified_imm function from all ARM instructions to just data ↵ | Gabe Black | |
| processing ones. | |||
| 2010-06-02 | ARM: Add new base classes for data processing instructions. | Gabe Black | |
| 2010-06-02 | ARM: Reimplement load/store multiple external to the decoder. | Gabe Black | |
| --HG-- rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/insts/macromem.isa rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/templates/macromem.isa | |||
| 2010-06-02 | ARM: Remove the special naming for the new memory instructions. | Gabe Black | |
| These are the only memory instructions now. | |||
| 2010-06-02 | ARM: Eliminate the old memory formats which are no longer used. | Gabe Black | |
| 2010-06-02 | ARM: Eliminate decoding for the very deprecated FPA instructions. | Gabe Black | |
| 2010-06-02 | ARM: Add a .w to the disassembly of 32 bit thumb instructions. | Gabe Black | |
| This isn't technically correct since the .w should only be added if there are 32 and 16 bit encodings, but always having it always is better than never having it. | |||
| 2010-06-02 | ARM: Implement a new set of base classes for non macro memory instructions. | Gabe Black | |
| 2010-06-02 | ARM: Replace the "never" condition with the "unconditional" condition. | Gabe Black | |
| 2010-06-02 | ARM: Add a base class for 32 bit thumb data processing immediate instructions. | Gabe Black | |
| 2010-06-02 | ARM: Add a function to decode 32 bit thumb immediate values. | Gabe Black | |
| 2010-06-02 | ARM: Make sure ExtMachInst is used consistently instead of regular MachInst. | Gabe Black | |
| 2010-06-02 | ARM: Add a new base class for instructions that can do an interworking branch. | Gabe Black | |
| 2010-06-02 | ARM: Track the current ISA mode using the PC. | Gabe Black | |
| 2009-11-17 | ARM: Begin implementing CP15 | Ali Saidi | |
| 2009-11-14 | ARM: Write some functions to write to the CPSR and SPSR for instructions. | Gabe Black | |
| 2009-11-08 | ARM: Support forcing load/store multiple to use user registers. | Gabe Black | |
| 2009-11-04 | build: fix compile problems pointed out by gcc 4.4 | Nathan Binkert | |
| 2009-07-08 | ARM: Move the memory microops out of the decoder and into the ISA desc. | Gabe Black | |
| 2009-07-08 | ARM: Move the integer microops out of the decoder and into the ISA desc. | Gabe Black | |
| 2009-07-08 | ARM: Improve memory instruction disassembly. | Gabe Black | |
| 2009-07-08 | ARM: Tune up predicated instruction decoding. | Gabe Black | |
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