gem5 - gem5

Age	Commit message (Expand)	Author
2014-04-29	arm: use condition code registers for ARM ISA	Curtis Dunham
2014-09-03	arm: ISA X31 destination register fix	Andrew Bardsley
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2012-03-19	gcc: Clean-up of non-C++0x compliant code, first steps	Andreas Hansson
2011-05-13	ARM: Further break up condition code into NZ, C, V bits.	Ali Saidi
2011-05-13	ARM: Remove the saturating (Q) condition code from the renamed register.	Ali Saidi
2011-05-13	ARM: Break up condition codes into normal flags, saturation, and simd.	Ali Saidi
2011-04-15	includes: sort all includes	Nathan Binkert
2011-03-17	ARM: Fix RFE macrop.	Matt Horsnell
2010-08-25	ARM: Seperate out the renamable bits in the FPSCR.	Gabe Black
2010-06-02	ARM: Allow flattening into any mode.	Gabe Black
2010-06-02	ARM: Eliminate the unused rhi and rlo operands.	Gabe Black
2009-11-10	ARM: Fix the integer register indexes.	Gabe Black
2009-11-08	ARM: Support forcing load/store multiple to use user registers.	Gabe Black
2009-11-08	ARM: Split the condition codes out of the CPSR.	Gabe Black
2009-11-08	ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.	Gabe Black
2009-11-08	ARM: Set up an intregs.hh for ARM.	Gabe Black