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path: root/src/arch/arm/intregs.hh
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2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
This patch cleans up a number of minor issues aiming to get closer to compliance with the C++0x standard as interpreted by gcc and clang (compile with std=c++0x and -pedantic-errors). In particular, the patch cleans up enums where the last item was succeded by a comma, namespaces closed by a curcly brace followed by a semi-colon, and the use of the GNU-extension typeof (replaced by templated functions). It does not address variable-length arrays, zero-size arrays, anonymous structs, range expressions in switch statements, and the use of long long. The generated CPU code also has a large number of issues that remain to be fixed, mainly related to overflows in implicit constant conversion (due to shifts).
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions.
2011-05-13ARM: Remove the saturating (Q) condition code from the renamed register.Ali Saidi
Move the saturating bit (which is also saturating) from the renamed register that holds the flags to the CPSR miscreg and adds a allows setting it in a similar way to the FP saturating registers. This removes a dependency in instructions that don't write, but need to preserve the Q bit.
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
This change splits out the condcodes from being one monolithic register into three blocks that are updated independently. This allows CPUs to not have to do RMW operations on the flags registers for instructions that don't write all flags.
2011-04-15includes: sort all includesNathan Binkert
2011-03-17ARM: Fix RFE macrop.Matt Horsnell
This changes the RFE macroop into 3 microops: URa = [sp]; URb = [sp+4]; // load CPSR,PC values from stack sp = sp + offset; // optionally auto-increment PC = URa; CPSR = URb; // write to the PC and CPSR. Importantly: - writing to PC is handled in the last micro-op. - loading occurs prior to state changes.
2010-08-25ARM: Seperate out the renamable bits in the FPSCR.Gabe Black
2010-06-02ARM: Allow flattening into any mode.Gabe Black
2010-06-02ARM: Eliminate the unused rhi and rlo operands.Gabe Black
2009-11-10ARM: Fix the integer register indexes.Gabe Black
The PC indexes in the various register sets was defined in the section for unaliased registers which was throwing off the indexing. This moves those where they belong. Also, to make detecting accesses to the PC easier and because it's in the same place in all modes, the intRegForceUser function now passes it through as index 15.
2009-11-08ARM: Support forcing load/store multiple to use user registers.Gabe Black
2009-11-08ARM: Split the condition codes out of the CPSR.Gabe Black
This allows those bits to be renamed while allowing the other fields to control the behavior of the processor.
2009-11-08ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.Gabe Black
2009-11-08ARM: Set up an intregs.hh for ARM.Gabe Black
Add constants for all the modes and registers, maps for aliasing, functions that use the maps and range check, and use a named constant instead of a magic number for the microcode register.