summaryrefslogtreecommitdiff
path: root/src/arch/arm/intregs.hh
AgeCommit message (Expand)Author
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
2011-05-13ARM: Remove the saturating (Q) condition code from the renamed register.Ali Saidi
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
2011-04-15includes: sort all includesNathan Binkert
2011-03-17ARM: Fix RFE macrop.Matt Horsnell
2010-08-25ARM: Seperate out the renamable bits in the FPSCR.Gabe Black
2010-06-02ARM: Allow flattening into any mode.Gabe Black
2010-06-02ARM: Eliminate the unused rhi and rlo operands.Gabe Black
2009-11-10ARM: Fix the integer register indexes.Gabe Black
2009-11-08ARM: Support forcing load/store multiple to use user registers.Gabe Black
2009-11-08ARM: Split the condition codes out of the CPSR.Gabe Black
2009-11-08ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.Gabe Black
2009-11-08ARM: Set up an intregs.hh for ARM.Gabe Black