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path: root/src/arch/arm/isa.cc
AgeCommit message (Expand)Author
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
2016-04-05mem: Remove threadId from memory request classMitch Hayenga
2015-10-09isa: Add parameter to pick different decoder inside ISARekai Gonzalez Alberquilla
2015-09-30isa,cpu: Add support for FS SMT InterruptsMitch Hayenga
2015-06-09arm: Delete debug print in initialization of hardware threadRune Holm
2015-05-23dev, arm: Refactor and clean up the generic timer modelAndreas Sandberg
2015-05-05arm: Remove unnecessary boot uncachabilityAndreas Hansson
2015-03-02arm: Don't truncate 16-bit ASIDs to 8 bitsAndreas Sandberg
2015-01-22mem: Clean up Request initialisationAndreas Hansson
2014-12-23arm: Add support for filtering in the PMUAndreas Sandberg
2014-10-29arm: Fix multi-system AArch64 boot w/caches.Ali Saidi
2014-10-16arm: Add a model of an ARM PMUv3Andreas Sandberg
2014-04-29arm: use condition code registers for ARM ISACurtis Dunham
2014-04-17arm: allow DC instructions by default so SE mode worksAli Saidi
2014-05-09arm: Panics in miscreg read functions can be tripped by O3 modelGeoffrey Blake
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2014-01-24arch: Make all register index flattening constAndreas Hansson
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-01-07arm: Remove the register mapping hack used when copying TCsAndreas Sandberg
2013-01-07arm: Make ID registers ISA parametersAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2013-01-04Decoder: Remove the thread context get/set from the decoder.Gabe Black
2013-01-04ARM: Keep a copy of the fpscr len and stride fields in the decoder.Gabe Black
2012-07-27ARM: fix value of MISCREG_CTR returned by readMiscReg()Anthony Gutierrez
2012-06-05ARM: Fix MPIDR and MIDR register implementation.Chander Sudanthi
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-03-02ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine.Ali Saidi
2012-03-01ARM: Add support for Versatile Express extended memory mapAli Saidi
2012-03-01ARM: Add limited CP14 support.Matt Horsnell
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2011-09-13ARM: Implement numcpus bits in L2CTLR register.Daniel Johnson
2011-08-19ARM: Mark some variables uncacheable until boot all CPUs are enabled.Ali Saidi
2011-08-19ARM: Add support for DIV/SDIV instructions.Ali Saidi
2011-07-15ARM: Add two unimplemented miscellaneous registers.Wade Walker
2011-05-13ARM: Remove the saturating (Q) condition code from the renamed register.Ali Saidi
2011-05-13ARM: Better RealView/Versatile EB platform support.Chander Sudanthi
2011-05-04ARM: Add support for MP misc regs and broadcast flushes.Ali Saidi
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-04ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.Ali Saidi
2011-04-04ARM: Cleanup and small fixes to some NEON ops to match the spec.William Wang
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
2011-03-17ARM: Implement the Instruction Set Attribute Registers (ISAR).Ali Saidi
2011-02-23ARM: Reset simulation statistics when pref counters are reset.Ali Saidi
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-11-15ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a...Ali Saidi
2010-11-15ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.Ali Saidi
2010-11-08ARM: Keep the warnings to a minimum.Ali Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black