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is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
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isa.cc
Age
Commit message (
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Author
2018-05-08
arch-arm: Map ID_x_EL1 registers to AArch32 version
Giacomo Travaglini
2018-04-19
arch-arm: Add ARMv8.1 TTBR1_EL2 register
Giacomo Travaglini
2018-04-18
arch-arm: Fix masking in CPACR_EL1
Chuan Zhu
2018-04-18
arch-arm: Mask out unsupported trapped exception handling bits
Chuan Zhu
2018-04-18
arch-arm: Correct masking of cp10 and cp11 in CPACR
Chuan Zhu
2018-04-18
arch-arm: Using explicit invalidation in TLB
Giacomo Travaglini
2018-04-06
arch-arm: Fix secure write of SCTLR when EL3 is AArch64
Giacomo Travaglini
2018-03-23
arch-arm: Distinguish IS TLBI from non-IS
Giacomo Travaglini
2018-03-23
arch-arm: Created function for TLB ASID Invalidation
Giacomo Travaglini
2018-03-12
arch-arm: Adding IPA-Based Invalidating instructions
Giacomo Travaglini
2018-03-12
arch-arm: Implement missing aarch32 TLBI registers
Giacomo Travaglini
2018-03-08
arch-arm: Fix FSC generation in AbortFault
Giacomo Travaglini
2018-02-16
arch-arm: Change ArmFault cast from reinterpret to static
Giacomo Travaglini
2018-02-08
arch-arm: Don't change PSTATE in Illegal Exception return
Giacomo Travaglini
2018-01-29
arch-arm: understandably initialize register permissions
Curtis Dunham
2018-01-29
arm: extend MiscReg metadata structures
Curtis Dunham
2018-01-29
arch-arm: understandably initialize register mappings
Curtis Dunham
2017-12-22
arch,cpu: "virtualize" the TLB interface.
Gabe Black
2017-12-14
misc: Updates for gcc7.2 for x86
Jason Lowe-Power
2017-07-05
cpu: Added interface for vector reg file
Rekai Gonzalez-Alberquilla
2017-02-09
arm: AArch64 report cache size correctly when reading CTR_EL0
Bjoern A. Zeeb
2016-11-09
style: [patch 1/22] use /r/3648/ to reorganize includes
Brandon Potter
2016-12-19
arm: provide correct timer availability in ID_PFR1 register
Curtis Dunham
2016-12-19
arm: compute ID_AA64PFR{0,1}_EL1 registers
Curtis Dunham
2016-12-19
arm: compute ID_PFR{0,1} registers
Curtis Dunham
2016-12-19
arm: miscreg refactoring
Curtis Dunham
2016-12-19
arm: audit SCTLR
Curtis Dunham
2016-12-19
arm: remove SCTLR.FI
Curtis Dunham
2016-12-19
arm: update AArch{64,32} register mappings
Curtis Dunham
2016-08-15
cpu, arch: fix the type used for the request flags
Nikos Nikoleris
2016-08-02
arm: Add TLBI instruction for stage 2 IPA's
Dylan Johnson
2016-08-02
arm: Fix EL perceived at TLB for address translation instructions
Dylan Johnson
2016-08-02
arm: add stage2 translation support
Dylan Johnson
2016-08-02
arm: enable EL2 support
Curtis Dunham
2016-08-02
arm: invalidate TLB miscreg cache on modification of HSCTLR
Dylan Johnson
2016-07-11
arm: Don't consult the TLB test iface for functional translations
Andreas Sandberg
2016-04-07
mem: Remove threadId from memory request class
Mitch Hayenga
2016-04-06
Revert power patch sets with unexpected interactions
Andreas Sandberg
2016-04-05
mem: Remove threadId from memory request class
Mitch Hayenga
2015-10-09
isa: Add parameter to pick different decoder inside ISA
Rekai Gonzalez Alberquilla
2015-09-30
isa,cpu: Add support for FS SMT Interrupts
Mitch Hayenga
2015-06-09
arm: Delete debug print in initialization of hardware thread
Rune Holm
2015-05-23
dev, arm: Refactor and clean up the generic timer model
Andreas Sandberg
2015-05-05
arm: Remove unnecessary boot uncachability
Andreas Hansson
2015-03-02
arm: Don't truncate 16-bit ASIDs to 8 bits
Andreas Sandberg
2015-01-22
mem: Clean up Request initialisation
Andreas Hansson
2014-12-23
arm: Add support for filtering in the PMU
Andreas Sandberg
2014-10-29
arm: Fix multi-system AArch64 boot w/caches.
Ali Saidi
2014-10-16
arm: Add a model of an ARM PMUv3
Andreas Sandberg
2014-04-29
arm: use condition code registers for ARM ISA
Curtis Dunham
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