gem5 - gem5

Age	Commit message (Expand)	Author
2011-03-17	ARM: Implement the Instruction Set Attribute Registers (ISAR).	Ali Saidi
2011-02-23	ARM: Reset simulation statistics when pref counters are reset.	Ali Saidi
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli
2010-11-15	ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a...	Ali Saidi
2010-11-15	ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.	Ali Saidi
2010-11-08	ARM: Keep the warnings to a minimum.	Ali Saidi
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-10-01	ARM: Clean up use of TBit and JBit.	Ali Saidi
2010-09-13	Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.	Gabe Black
2010-08-25	ARM: Set the high bits in the part number so it's considered new by some code.	Ali Saidi
2010-08-25	ARM: Fix VFP enabled checks for mem instructions	Ali Saidi
2010-08-25	ARM: Implement CPACR register and return Undefined Instruction when FP access...	Gabe Black
2010-08-23	ARM: Clean up flattening for SPSR adding	Min Kyu Jeong
2010-08-23	ARM: Get SCTLR TE bit from reset SCTLR	Gene Wu
2010-08-23	ARM: We don't currently support ThumbEE exceptions, so don't report that we do	Ali Saidi
2010-08-23	ARM: Implement some more misc registers	Ali Saidi
2010-06-03	ARM: Fix issue with m5.fast and ARM	Ali Saidi
2010-06-02	ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PC...	Dam Sunwoo
2010-06-02	ARM: Move the ISA "clear" function into isa.cc.	Gabe Black
2010-06-02	ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.	Gabe Black
2010-06-02	ARM: Some TLB bug fixes.	Ali Saidi
2010-06-02	ARM: Move Miscreg functions out of isa.hh	Ali Saidi