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path: root/src/arch/arm/isa.cc
AgeCommit message (Expand)Author
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-01-07arm: Remove the register mapping hack used when copying TCsAndreas Sandberg
2013-01-07arm: Make ID registers ISA parametersAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2013-01-04Decoder: Remove the thread context get/set from the decoder.Gabe Black
2013-01-04ARM: Keep a copy of the fpscr len and stride fields in the decoder.Gabe Black
2012-07-27ARM: fix value of MISCREG_CTR returned by readMiscReg()Anthony Gutierrez
2012-06-05ARM: Fix MPIDR and MIDR register implementation.Chander Sudanthi
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-03-02ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine.Ali Saidi
2012-03-01ARM: Add support for Versatile Express extended memory mapAli Saidi
2012-03-01ARM: Add limited CP14 support.Matt Horsnell
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2011-09-13ARM: Implement numcpus bits in L2CTLR register.Daniel Johnson
2011-08-19ARM: Mark some variables uncacheable until boot all CPUs are enabled.Ali Saidi
2011-08-19ARM: Add support for DIV/SDIV instructions.Ali Saidi
2011-07-15ARM: Add two unimplemented miscellaneous registers.Wade Walker
2011-05-13ARM: Remove the saturating (Q) condition code from the renamed register.Ali Saidi
2011-05-13ARM: Better RealView/Versatile EB platform support.Chander Sudanthi
2011-05-04ARM: Add support for MP misc regs and broadcast flushes.Ali Saidi
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-04ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.Ali Saidi
2011-04-04ARM: Cleanup and small fixes to some NEON ops to match the spec.William Wang
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
2011-03-17ARM: Implement the Instruction Set Attribute Registers (ISAR).Ali Saidi
2011-02-23ARM: Reset simulation statistics when pref counters are reset.Ali Saidi
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-11-15ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a...Ali Saidi
2010-11-15ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.Ali Saidi
2010-11-08ARM: Keep the warnings to a minimum.Ali Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-10-01ARM: Clean up use of TBit and JBit.Ali Saidi
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
2010-08-25ARM: Set the high bits in the part number so it's considered new by some code.Ali Saidi
2010-08-25ARM: Fix VFP enabled checks for mem instructionsAli Saidi
2010-08-25ARM: Implement CPACR register and return Undefined Instruction when FP access...Gabe Black
2010-08-23ARM: Clean up flattening for SPSR addingMin Kyu Jeong
2010-08-23ARM: Get SCTLR TE bit from reset SCTLRGene Wu
2010-08-23ARM: We don't currently support ThumbEE exceptions, so don't report that we doAli Saidi
2010-08-23ARM: Implement some more misc registersAli Saidi
2010-06-03ARM: Fix issue with m5.fast and ARMAli Saidi
2010-06-02ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PC...Dam Sunwoo
2010-06-02ARM: Move the ISA "clear" function into isa.cc.Gabe Black
2010-06-02ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.Gabe Black
2010-06-02ARM: Some TLB bug fixes.Ali Saidi
2010-06-02ARM: Move Miscreg functions out of isa.hhAli Saidi