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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
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arm
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isa.cc
Age
Commit message (
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Author
2010-08-25
ARM: Set the high bits in the part number so it's considered new by some code.
Ali Saidi
2010-08-25
ARM: Fix VFP enabled checks for mem instructions
Ali Saidi
2010-08-25
ARM: Implement CPACR register and return Undefined Instruction when FP access...
Gabe Black
2010-08-23
ARM: Clean up flattening for SPSR adding
Min Kyu Jeong
2010-08-23
ARM: Get SCTLR TE bit from reset SCTLR
Gene Wu
2010-08-23
ARM: We don't currently support ThumbEE exceptions, so don't report that we do
Ali Saidi
2010-08-23
ARM: Implement some more misc registers
Ali Saidi
2010-06-03
ARM: Fix issue with m5.fast and ARM
Ali Saidi
2010-06-02
ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PC...
Dam Sunwoo
2010-06-02
ARM: Move the ISA "clear" function into isa.cc.
Gabe Black
2010-06-02
ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.
Gabe Black
2010-06-02
ARM: Some TLB bug fixes.
Ali Saidi
2010-06-02
ARM: Move Miscreg functions out of isa.hh
Ali Saidi