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2018-11-14arch-arm: Print register name when warning on AT instructionsGiacomo Travaglini
With this patch we don't print anymore the enum value when warning on any AT instruction usage, but we print the sys reg name instead Change-Id: Ic6831b98ad6b0582be69883dc9519a9d3324da30 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14316 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-07arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32Giacomo Travaglini
ARMv8 differs from ARMv7 with the presence of RVBAR register, which contains the implementation defined reset address when EL3 is not implemented. The entry 0x0 in the AArch32 vector table, once used for the Reset Vector, is now marked as "Not used", stating that it is now IMPLEMENTATION DEFINED. An implementation might still use this vector table entry to hold the Reset vector, but having a Reset address != than the general vector table (for any other exception) is allowed. At the moment any Reset exception is still using 0 as a vector table base address. This patch is extending the ArmSystem::resetAddr64 to ArmSystem::resetAddr so that it can be used for initializing MVBAR/RVBAR. In order to do so, we are providing a specialized behavior for the Reset exception when evaluating the vector base address. Change-Id: I051a730dc089e194db3b107bbed19251c661f87e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14000 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-11-07arch-arm: Refactor ISA::clear by adding a ISA::clear32 methodGiacomo Travaglini
The patch is also moving some initialization code to be used by AArch64 as well since the registers are mapped to AArch64 ones. Change-Id: I0089df25275434172c6e0e9cb125ee535c04d1b8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13997 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-09arch-arm: Add have_crypto System parameterGiacomo Travaglini
This patch adds the have_crypto ArmSystem parameter for enabling crypto extension. This is done by modifying the AArch32/AArch64 ID registers at startup time. Change-Id: I6eefb7e6f6354802a14ea639ad53b75f8e1e11c5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13252 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-01arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 registerGiacomo Travaglini
This patch implements AArch64 Memory Model Feature Register 2 (from ARMv8.2) Change-Id: I16d9acaf620fac6d1206e208bd143daec1657daf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13066 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01arch-arm: Init AArch64 ID registers in SE modeGiacomo Travaglini
One of the auxv vector's flag is the HWCAP, whose bits match the content of several arm ID registers. This patch factors out AArch64 ID registers init into a separate method and creates the symmetric AArch32 ID register init as well, so that we get a meaningful auxiliary vector in SE mode. Change-Id: I52bdb31b67508c4447558ebd7ca743733a69280e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13064 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-10arm: Add support for tracking TCs in ISA devicesAndreas Sandberg
ISA devices typically need to keep track of the thread context they are associated with. Among other things, this is required for interrupt delivery. Add a BaseISADevice:setThreadContext() method to wire such models to the right thread context. Change-Id: Iad354d176c0c4c4e34c6ab8b5acaee0b69da0406 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12399 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-07-16arch-arm: Introduce ARMv8.1 Virtual Timer System RegistersGiacomo Travaglini
Adding CNTHV_CTL_EL2, CNTHV_CVAL_EL2, CNTHV_TVAL_EL2 System Registers into the decode tree. They are currently implemented as a generic timer and produces a warning if accessed. Change-Id: I1a23035d67f95eeac49d890283e9a0d58426d504 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11592 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-14arch-arm: Add Illegal Execution flag to PCStateGiacomo Travaglini
This patch moves the detection of the Illegal Execution flag (PSTATE.IL) from the tlb translation stage (fetch) to the decoding stage. This is done by adding the illegalExecution field to the PCState. Change-Id: I9c1c4e9c6bd5ded905c1d56b3034e4e9322582fa Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10813 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
This patch is changing the underlying type for RequestPtr from Request* to shared_ptr<Request>. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers. Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-29arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOPGiacomo Travaglini
In the Arm ISA there are some sys reg numbers which are reserved for implementation defined registers. The default behaviour is to to treat them as unimplemented registers. It is now possible to change this behaviour at runtime and treat them as NOP. In this way an access to those register won't make simulation fail. Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10504 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-08arch-arm: Map ID_x_EL1 registers to AArch32 versionGiacomo Travaglini
AArch64 ID_x_EL1 registers map to AArch32 ID_x counterparts. Those registers must be initialized even when the highest Exception Level is using AArch64. Change-Id: Iccc9b6f631f5fac288116eb1ef2ad1d30c03de7b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10361 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-19arch-arm: Add ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
This patch adds ARMv8.1 TTBR1_EL2 register into the decodeAArch64SysReg table, but stil leaving it unimplemented (Accessing it through MSR/MRS causes an exception) Change-Id: I463b86cc544233aa1ee5b2fcba689d6b9f2a874b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10063 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18arch-arm: Fix masking in CPACR_EL1Chuan Zhu
Some bits in CPACR_EL1 are RES0 but not RAZ/WI. For instance, bit CPACR_EL1[31] is RES0 but should be made stateful, since it allows programing of CPACR.ASEDIS. Therefore the masking of CPACR_EL1 is removed. Change-Id: If1fa3fa1e06bc38495b8afce2c635f3ddf76ce32 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10046 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18arch-arm: Mask out unsupported trapped exception handling bitsChuan Zhu
Floating-point trapped exception handlings are not currently supported in gem5, therefore the corresponding bits are RAZ/WI in FCPR. Change-Id: Ica43af62d5f3bbc095e8dd872f0bd365231a5b5f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10045 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18arch-arm: Correct masking of cp10 and cp11 in CPACRChuan Zhu
This patch fixes the masking of cp10 and cp11 in CPACR according to NSACR.cp10 / NSACR.cp11 by adding the condition "in Non-secure state, if EL3 is implemented and is using AArch32...", which is specified in ARM ARM. Change-Id: Id00e7bf04d6a985e27dbf1028677da0746b79924 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10044 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-18arch-arm: Using explicit invalidation in TLBGiacomo Travaglini
When setting TLB related MiscRegs, using explicit TLB regs invalidation rather than implicit switch-case fallthrough Change-Id: Ia1a7358b6d54dda3811be1c5ce5d676f8c518c4d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10041 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-06arch-arm: Fix secure write of SCTLR when EL3 is AArch64Giacomo Travaglini
MiscRegisters are not banked between secure and non-secure mode if EL3 is not implemented or if EL3 is using AArch64 (highestELIs64). In this scenario a unique register is used and it is mapped to the NS version (see snsBankedIndex implementation), so that a secure world read/write should access the non secure storage. Change-Id: Ica4182e3cdf4021d2bd1db23e477ce2bbf055926 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9502 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-23arch-arm: Distinguish IS TLBI from non-ISGiacomo Travaglini
TLBI broadcasting was the default implementation of most of TLBI instructions. This patch applies the broadcasting behaviour only to the Inner-Shareable subset, while simpler TLB invalidation instructions only affect the PE that executes them. Change-Id: Idb01d0d4f593131f657e8fc9668112de8e4ccdcb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9182 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-23arch-arm: Created function for TLB ASID InvalidationGiacomo Travaglini
This patch is intended to avoid code duplication and extends the set of TLBI ISA functions adding the entry invalidation by ASID match. Change-Id: I9bcb498059ea480dd2118639c7b3c64fea80a5e1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9181 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-12arch-arm: Adding IPA-Based Invalidating instructionsGiacomo Travaglini
This patch introduces the TLB IPA-Based invalidating instructions in aarch32. In the entry selection policy the level of translation is not taken into account. This means that no difference stands between (e.g.) TLBIIPAS2 and TLBIPAS2L. Change-Id: Ieeb54665480874d2041056f356d86448c45043cb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8822 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-12arch-arm: Implement missing aarch32 TLBI registersGiacomo Travaglini
In the pool of TLB Invalidate system register a category of instruction was missing: the ones operating on entries added to the TLB during the last level only of a table walk. (E.g. TLBIVMAL). This patch is not considering this matching criteria when invalidating the entries and it is rather performing the invalidation on all levels. Change-Id: I5f2186cfdd73793e76c90b260f7128be187903fe Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8821 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-08arch-arm: Fix FSC generation in AbortFaultGiacomo Travaglini
The fault status code generated by a Prefetch/Data Fault was containing a wrong value when the fault was triggered in aarch32 but handled in aarch64. This because the encoding differs between the two ISAs and the encoder was just checking the starting ISA rather than the the ending one. In this case the getFsr must be called after we know which is the ending ISA, which happens only after ArmFault::invoke gets called. The fsc update hence happens before writing into the Syndrome register. Change-Id: I725f12b6dcc0178f608233bd3d15e466d1cd1ffc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8362 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-16arch-arm: Change ArmFault cast from reinterpret to staticGiacomo Travaglini
Changing casting type in src/arch/arm/isa.cc Change-Id: Ia19b30a1bf8b1b25df149b52613a3533eaced03a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8241 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-08arch-arm: Don't change PSTATE in Illegal Exception returnGiacomo Travaglini
This patch fixes the Illegal Exception return handler. According to the armarm documentation, when PSTATE.IL is set to one because of an illegal exception return, PSTATE.{EL, nRW, SP} are unchanged. This means the Exception level, Execution state, and stack pointer selection do not change as a result of the return. Change-Id: I35f2fe68fb2822a54fc4a21930871eab7a1aaab4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8021 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29arch-arm: understandably initialize register permissionsCurtis Dunham
Move massive initialization routine to the bottom of miscregs.cc. Additionally, share register metadata across ISA instances by making lookUpMiscReg a static member of the ISA and only initializing it once. Change-Id: I6d6ab26200c4e781151cc6efd97ce2420e2bf4cc Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6803 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29arm: extend MiscReg metadata structuresCurtis Dunham
Implement proper handling of RES0/RES1 and RAZ/RAO bitfields. Change-Id: I344c32c3fb1d142acfb0521ba3590ddd2b1f5360 Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6802 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-29arch-arm: understandably initialize register mappingsCurtis Dunham
The mappings for sharing a backing store between AArch32 and AArch64 system registers are made clearer using an initializer object. Change-Id: I29dcfab2797b4d36b3182342997edffde334a291 Signed-off-by: Curtis Dunham <Curtis.Dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6801 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
CPUs have historically instantiated the architecture specific version of the TLBs to avoid a virtual function call, making them a little bit more dependent on what the current ISA is. Some simple performance measurement, the x86 twolf regression on the atomic CPU, shows that there isn't actually any performance benefit, and if anything the simulator goes slightly faster (although still within margin of error) when the TLB functions are virtual. This change switches everything outside of the architectures themselves to use the generic BaseTLB type, and then inside the ISA for them to cast that to their architecture specific type to call into architecture specific interfaces. The ARM TLB needed the most adjustment since it was using non-standard translation function signatures. Specifically, they all took an extra "type" parameter which defaulted to normal, and translateTiming returned a Fault. translateTiming actually doesn't need to return a Fault because everywhere that consumed it just stored it into a structure which it then deleted(?), and the fault is stored in the Translation object when the translation is done. A little more work is needed to fully obviate the arch/tlb.hh header, so the TheISA::TLB type is still visible outside of the ISAs. Specifically, the TlbEntry type is used in the generic PageTable which lives in src/mem. Change-Id: I51b68ee74411f9af778317eff222f9349d2ed575 Reviewed-on: https://gem5-review.googlesource.com/6921 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-14misc: Updates for gcc7.2 for x86Jason Lowe-Power
GCC 7.2 is much stricter than previous GCC versions. The following changes are needed: * There is now a warning if there is an implicit fallthrough between two case statments. C++17 adds the [[fallthrough]]; declaration. However, to support non C++17 standards (i.e., C++11), we use M5_FALLTHROUGH. M5_FALLTHROUGH checks for [[fallthrough]] compliant C++17 compiler and if that doesn't exist, it defaults to nothing (no older compilers generate warnings). * The above resulted in a couple of bugs that were found. This is noted in the review request on gerrit. * throw() for dynamic exception specification is deprecated * There were a couple of new uninitialized variable warnings * Can no longer perform bitwise operations on a bool. * Must now include <functional> for std::function * Compiler bug for void* lambda. Changed to auto as work around. See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82878 Change-Id: I5d4c782a4e133fa4cdb119e35d9aff68c6e2958e Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/5802 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
This patch adds some more functionality to the cpu model and the arch to interface with the vector register file. This change consists mainly of augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation. This requires implementing the vector register file for the different models using the VecRegContainer class. This change set also updates the Result abstraction to contemplate the possibility of having a vector as result. The changes also affect how the remote_gdb connection works. There are some (nasty) side effects, such as the need to define dummy numPhysVecRegs parameter values for architectures that do not implement vector extensions. Nathanael Premillieu's work with an increasing number of fixes and improvements of mine. Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues and CC reg free list initialisation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2705
2017-02-09arm: AArch64 report cache size correctly when reading CTR_EL0Bjoern A. Zeeb
Trying to read MISCREG_CTR_EL0 on AArch64 returned 0 as is was not implmemented. With that an operating system relying on the cache line sizes reported in order to manage the caches would (a) panic given the returned value 0 is not valid (high bit is RES1) or (b) worst case would assume a cache line size of 4 doing a tremendous amount of extra instruction work (including fetching). Return the same values as for ARMv7 as the fields seem to be the same, or RES0/1 seem to be reported accordingly for AArch64 In collaboration with: Andrew Turner Testing Done: Checked on FreeBSD boots with extra printfs; also observed a reduction of a factor of about 10 in instruction fetches for a simple micro-test. Reviewed at http://reviews.gem5.org/r/3667/ Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2016-12-19arm: provide correct timer availability in ID_PFR1 registerCurtis Dunham
Change-Id: Id4cd839c12b70616017a5830e3f9bbb59b0f97ba Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-12-19arm: compute ID_AA64PFR{0,1}_EL1 registersCurtis Dunham
Compute the proper values of the aforementioned registers from the system configuration rather than configuring the values themselves. Change-Id: If9774b6610a29568b80ae4866107b9a6a5b5be0f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-12-19arm: compute ID_PFR{0,1} registersCurtis Dunham
Compute the proper values of the aforementioned registers from the system configuration rather than configuring the values themselves. Change-Id: Ie7685b5d8b5f2dd9d6380b4af74f16d596b2bfd1 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-12-19arm: miscreg refactoringCurtis Dunham
Change-Id: I4e9e8f264a4a4239dd135a6c7a1c8da213b6d345 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-12-19arm: audit SCTLRCurtis Dunham
Change-Id: I814f1431a5f754f75721c9ac51171f860a714d24 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-12-19arm: remove SCTLR.FICurtis Dunham
Removed from ARMARM. Change-Id: Ie8f28e4fa6e1b46dfd9c8c4b379e5b42fe25421d Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-12-19arm: update AArch{64,32} register mappingsCurtis Dunham
Change-Id: Idaaaeb3f7b1a0bdbf18d8e2d46686c78bb411317 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
Change-Id: I183b9942929c873c3272ce6d1abd4ebc472c7132 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-02arm: Add TLBI instruction for stage 2 IPA'sDylan Johnson
This patch adds support for stage 2 TLBI instructions such as TLBI IPAS2E1_Xt. Change-Id: I0cd5e8055b0c1003e03439aa5183252f50ea0a88
2016-08-02arm: Fix EL perceived at TLB for address translation instructionsDylan Johnson
During address translation instructions (such as AT S1E1R_Xt) the exception level can be different than the current exception level. This patch fixes how the TLB determines what EL to use during these instructions. Change-Id: Ia9ce229404de9e284bc1f7479fd2c580efd55f8f
2016-08-02arm: add stage2 translation supportDylan Johnson
Change-Id: I8f7c09c7ec3a97149ebebf4b21471b244e6cecc1
2016-08-02arm: enable EL2 supportCurtis Dunham
Change-Id: I59fa4fae98c33d9e5c2185382e1411911d27d341
2016-08-02arm: invalidate TLB miscreg cache on modification of HSCTLRDylan Johnson
Change-Id: I5212c91c56435fe008950ed99feacc6921609226
2016-07-11arm: Don't consult the TLB test iface for functional translationsAndreas Sandberg
Don't consult the TLB test interface for PA's returned by functional translations by the AT instruction. We implement this by chaning the ISA code to synthesize 0-length functional reads for the TLB lookup. The TLB then bypasses the final PA check in the tester if the size is zero. Change-Id: I2487b7f829cea88c37e229e9fc7a4543aced961b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu. This is a re-spin of 20264eb after the revert (bd1c6789) and includes some fixes of that commit.
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
The following patches had unexpected interactions with the current upstream code and have been reverted for now: e07fd01651f3: power: Add support for power models 831c7f2f9e39: power: Low-power idle power state for idle CPUs 4f749e00b667: power: Add power states to ClockedObject Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> --HG-- extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508
2016-04-05mem: Remove threadId from memory request classMitch Hayenga
In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu.
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