gem5 - gem5

Age	Commit message (Expand)	Author
2016-08-02	arm: add stage2 translation support	Dylan Johnson
2016-08-02	arm: enable EL2 support	Curtis Dunham
2016-08-02	arm: invalidate TLB miscreg cache on modification of HSCTLR	Dylan Johnson
2016-07-11	arm: Don't consult the TLB test iface for functional translations	Andreas Sandberg
2016-04-07	mem: Remove threadId from memory request class	Mitch Hayenga
2016-04-06	Revert power patch sets with unexpected interactions	Andreas Sandberg
2016-04-05	mem: Remove threadId from memory request class	Mitch Hayenga
2015-10-09	isa: Add parameter to pick different decoder inside ISA	Rekai Gonzalez Alberquilla
2015-09-30	isa,cpu: Add support for FS SMT Interrupts	Mitch Hayenga
2015-06-09	arm: Delete debug print in initialization of hardware thread	Rune Holm
2015-05-23	dev, arm: Refactor and clean up the generic timer model	Andreas Sandberg
2015-05-05	arm: Remove unnecessary boot uncachability	Andreas Hansson
2015-03-02	arm: Don't truncate 16-bit ASIDs to 8 bits	Andreas Sandberg
2015-01-22	mem: Clean up Request initialisation	Andreas Hansson
2014-12-23	arm: Add support for filtering in the PMU	Andreas Sandberg
2014-10-29	arm: Fix multi-system AArch64 boot w/caches.	Ali Saidi
2014-10-16	arm: Add a model of an ARM PMUv3	Andreas Sandberg
2014-04-29	arm: use condition code registers for ARM ISA	Curtis Dunham
2014-04-17	arm: allow DC instructions by default so SE mode works	Ali Saidi
2014-05-09	arm: Panics in miscreg read functions can be tripped by O3 model	Geoffrey Blake
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2014-01-24	arch: Make all register index flattening const	Andreas Hansson
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-01-07	arm: Remove the register mapping hack used when copying TCs	Andreas Sandberg
2013-01-07	arm: Make ID registers ISA parameters	Andreas Sandberg
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2013-01-04	Decoder: Remove the thread context get/set from the decoder.	Gabe Black
2013-01-04	ARM: Keep a copy of the fpscr len and stride fields in the decoder.	Gabe Black
2012-07-27	ARM: fix value of MISCREG_CTR returned by readMiscReg()	Anthony Gutierrez
2012-06-05	ARM: Fix MPIDR and MIDR register implementation.	Chander Sudanthi
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-03-02	ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine.	Ali Saidi
2012-03-01	ARM: Add support for Versatile Express extended memory map	Ali Saidi
2012-03-01	ARM: Add limited CP14 support.	Matt Horsnell
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2011-09-13	ARM: Implement numcpus bits in L2CTLR register.	Daniel Johnson
2011-08-19	ARM: Mark some variables uncacheable until boot all CPUs are enabled.	Ali Saidi
2011-08-19	ARM: Add support for DIV/SDIV instructions.	Ali Saidi
2011-07-15	ARM: Add two unimplemented miscellaneous registers.	Wade Walker
2011-05-13	ARM: Remove the saturating (Q) condition code from the renamed register.	Ali Saidi
2011-05-13	ARM: Better RealView/Versatile EB platform support.	Chander Sudanthi
2011-05-04	ARM: Add support for MP misc regs and broadcast flushes.	Ali Saidi
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-04	ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.	Ali Saidi
2011-04-04	ARM: Cleanup and small fixes to some NEON ops to match the spec.	William Wang
2011-04-04	ARM: Cleanup implementation of ITSTATE and put important code in PCState.	Ali Saidi
2011-03-17	ARM: Implement the Instruction Set Attribute Registers (ISAR).	Ali Saidi
2011-02-23	ARM: Reset simulation statistics when pref counters are reset.	Ali Saidi
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli