| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2013-01-07 | arch: Move the ISA object to a separate section | Andreas Sandberg | |
| After making the ISA an independent SimObject, it is serialized automatically by the Python world. Previously, this just resulted in an empty ISA section. This patch moves the contents of the ISA to that section and removes the explicit ISA serialization from the thread contexts, which makes it behave like a normal SimObject during serialization. Note: This patch breaks checkpoint backwards compatibility! Use the cpt_upgrader.py utility to upgrade old checkpoints to the new format. | |||
| 2013-01-07 | arch: Make the ISA class inherit from SimObject | Andreas Sandberg | |
| The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU. | |||
| 2011-04-15 | trace: reimplement the DTRACE function so it doesn't use a vector | Nathan Binkert | |
| At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help | |||
| 2010-11-08 | ARM: Add checkpointing support | Ali Saidi | |
| 2010-08-23 | ARM: Clean up flattening for SPSR adding | Min Kyu Jeong | |
| 2010-06-02 | ARM: Move the ISA "clear" function into isa.cc. | Gabe Black | |
| 2010-06-02 | ARM: Some TLB bug fixes. | Ali Saidi | |
| 2010-06-02 | ARM: Move Miscreg functions out of isa.hh | Ali Saidi | |
| 2010-06-02 | ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements. | Ali Saidi | |
| 2010-06-02 | ARM: Implement ARM CPU interrupts | Ali Saidi | |
| 2010-06-02 | ARM: Make various bits of the FP control registers read only. | Gabe Black | |
| 2010-06-02 | ARM: Make MPIDR return 0 and ignore writes. | Gabe Black | |
| 2010-06-02 | ARM: Set the value of the MVFR0 and MVFR1 registers. | Gabe Black | |
| 2010-06-02 | ARM: Handle accesses to TLBTR. | Gabe Black | |
| 2010-06-02 | ARM: Convert the CP15 registers from MPU to MMU. | Gabe Black | |
| 2010-06-02 | ARM: Add some support for wfi/wfe/yield/etc | Ali Saidi | |
| 2010-06-02 | ARM: Add a traceflag to print cpsr | Ali Saidi | |
| 2010-06-02 | ARM: Ignore attempts to disable coprocessors that aren't implemented anyway. | Gabe Black | |
| 2010-06-02 | ARM: Allow flattening into any mode. | Gabe Black | |
| 2010-06-02 | ARM: Make the MPUIR register report that 1 unified data region is supported. | Gabe Black | |
| 2010-06-02 | ARM: Ignore/warn when CSSELR or CCSIDR are accessed. | Gabe Black | |
| These registers provide information about the caches. Since we can't provide that information, these will be harmlessly inert. | |||
| 2010-06-02 | ARM: Add support for the clidr register. | Gabe Black | |
| This register will always report 0 caches as implemented. It's not clear how to find out how many there really are when dealing with an arbitrary hierarchy. | |||
| 2010-06-02 | ARM: Implement a stub of CPACR. | Gabe Black | |
| This register controls access to the coprocessors. This doesn't actually implement it, it allows writes which don't turn anything off. In other words, it allows the simulated program to ask for what it already has. | |||
| 2010-06-02 | ARM: Actually write the value of sctlr in ISA.clear(). | Gabe Black | |
| 2010-06-02 | ARM: Implement a function to decode CP15 registers to MiscReg indices. | Gabe Black | |
| 2010-06-02 | ARM: Track the current ISA mode using the PC. | Gabe Black | |
| 2009-11-14 | ARM: Hook up the moded versions of the SPSR. | Gabe Black | |
| These registers can be accessed directly, or through MISCREG_SPSR which will act as whichever SPSR is appropriate for the current mode. | |||
| 2009-11-10 | ARM: Implement fault classes. | Gabe Black | |
| Implement some fault classes using the curriously recurring template pattern, similar to SPARCs. | |||
| 2009-11-08 | ARM: Support forcing load/store multiple to use user registers. | Gabe Black | |
| 2009-11-08 | ARM: Add in more bits for the mon mode. | Gabe Black | |
| 2009-11-08 | ARM: Initialize processes in user mode. | Gabe Black | |
| I accidentally left in a change to test using int registers in system mode. This change reverts that. | |||
| 2009-11-08 | ARM: Implement the shadow registers using register flattening. | Gabe Black | |
| 2009-10-17 | ISA: Fix compilation. | Gabe Black | |
| 2009-07-27 | ARM: Initialize the CPSR so that we're in user mode. | Gabe Black | |
| 2009-07-09 | ARM: Fold the MiscRegFile all the way into the ISA object. | Gabe Black | |
| 2009-07-08 | Registers: Collapse ARM and MIPS regfile directories. | Gabe Black | |
| --HG-- rename : src/arch/arm/regfile/misc_regfile.hh => src/arch/arm/misc_regfile.hh rename : src/arch/arm/regfile/regfile.cc => src/arch/arm/regfile.cc rename : src/arch/mips/regfile/misc_regfile.cc => src/arch/mips/misc_regfile.cc rename : src/arch/mips/regfile/misc_regfile.hh => src/arch/mips/misc_regfile.hh | |||
| 2009-07-08 | Registers: Add an ISA object which replaces the MiscRegFile. | Gabe Black | |
| This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU. | |||
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