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path: root/src/arch/arm/isa.hh
AgeCommit message (Expand)Author
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
2016-12-19arm: miscreg refactoringCurtis Dunham
2016-12-19arm: update AArch{64,32} register mappingsCurtis Dunham
2016-08-02arm: enable EL2 supportCurtis Dunham
2015-10-09isa: Add parameter to pick different decoder inside ISARekai Gonzalez Alberquilla
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-05-23dev, arm: Refactor and clean up the generic timer modelAndreas Sandberg
2015-05-05arm: Remove unnecessary boot uncachabilityAndreas Hansson
2015-03-02arm: Don't truncate 16-bit ASIDs to 8 bitsAndreas Sandberg
2014-10-29arm: Fix multi-system AArch64 boot w/caches.Ali Saidi
2014-10-16arm: Add a model of an ARM PMUv3Andreas Sandberg
2014-04-29arm: use condition code registers for ARM ISACurtis Dunham
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2014-01-24arch: Make all register index flattening constAndreas Hansson
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-02-19scons: Add warning for overloaded virtual functionsAndreas Hansson
2013-01-12x86: Changes to decoder, corrects 9376Nilay Vaish
2013-01-07arch: Move the ISA object to a separate sectionAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2010-11-08ARM: Add checkpointing supportAli Saidi
2010-08-23ARM: Clean up flattening for SPSR addingMin Kyu Jeong
2010-06-02ARM: Move the ISA "clear" function into isa.cc.Gabe Black
2010-06-02ARM: Some TLB bug fixes.Ali Saidi
2010-06-02ARM: Move Miscreg functions out of isa.hhAli Saidi
2010-06-02ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.Ali Saidi
2010-06-02ARM: Implement ARM CPU interruptsAli Saidi
2010-06-02ARM: Make various bits of the FP control registers read only.Gabe Black
2010-06-02ARM: Make MPIDR return 0 and ignore writes.Gabe Black
2010-06-02ARM: Set the value of the MVFR0 and MVFR1 registers.Gabe Black
2010-06-02ARM: Handle accesses to TLBTR.Gabe Black
2010-06-02ARM: Convert the CP15 registers from MPU to MMU.Gabe Black
2010-06-02ARM: Add some support for wfi/wfe/yield/etcAli Saidi
2010-06-02ARM: Add a traceflag to print cpsrAli Saidi
2010-06-02ARM: Ignore attempts to disable coprocessors that aren't implemented anyway.Gabe Black
2010-06-02ARM: Allow flattening into any mode.Gabe Black
2010-06-02ARM: Make the MPUIR register report that 1 unified data region is supported.Gabe Black
2010-06-02ARM: Ignore/warn when CSSELR or CCSIDR are accessed.Gabe Black
2010-06-02ARM: Add support for the clidr register.Gabe Black
2010-06-02ARM: Implement a stub of CPACR.Gabe Black
2010-06-02ARM: Actually write the value of sctlr in ISA.clear().Gabe Black
2010-06-02ARM: Implement a function to decode CP15 registers to MiscReg indices.Gabe Black
2010-06-02ARM: Track the current ISA mode using the PC.Gabe Black
2009-11-14ARM: Hook up the moded versions of the SPSR.Gabe Black
2009-11-10ARM: Implement fault classes.Gabe Black
2009-11-08ARM: Support forcing load/store multiple to use user registers.Gabe Black
2009-11-08ARM: Add in more bits for the mon mode.Gabe Black
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