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path: root/src/arch/arm/isa.hh
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2015-05-23dev, arm: Refactor and clean up the generic timer modelAndreas Sandberg
This changeset cleans up the generic timer a bit and moves most of the register juggling from the ISA code into a separate class in the same source file as the rest of the generic timer. It also removes the assumption that there is always 8 or fewer CPUs in the system. Instead of having a fixed limit, we now instantiate per-core timers as they are requested. This is all in preparation for other patches that add support for virtual timers and a memory mapped interface.
2015-05-05arm: Remove unnecessary boot uncachabilityAndreas Hansson
With the recent patches addressing how we deal with uncacheable accesses there is no longer need for the work arounds put in place to enforce certain sections of memory to be uncacheable during boot.
2015-03-02arm: Don't truncate 16-bit ASIDs to 8 bitsAndreas Sandberg
The ISA code sometimes stores 16-bit ASIDs as 8-bit unsigned integers and has a couple of inverted checks that mask out the high 8 bits of an ASID if 16-bit ASIDs have been /enabled/. This changeset fixes both of those issues.
2014-10-29arm: Fix multi-system AArch64 boot w/caches.Ali Saidi
Automatically extract cpu release address from DTB file. Check SCTLR_EL1 to verify all caches are enabled.
2014-10-16arm: Add a model of an ARM PMUv3Andreas Sandberg
This class implements a subset of the ARM PMU v3 specification as described in the ARMv8 reference manual. It supports most of the features of the PMU, however the following features are known to be missing: * Event filtering (e.g., from different privilege levels). * Access controls (the PMU currently ignores the execution level). * The chain counter (event no. 0x1E) is unimplemented. The PMU itself does not implement any events, it merely provides an interface for the configuration scripts to hook up probes that drive events. Configuration scripts should call addEventProbe() to configure custom events or high-level methods to configure architected events. The Python implementation of addEventProbe() automatically delays event type registration until after instantiation. In order to support CPU switching and some combined counters (e.g., memory references synthesized from loads and stores), the PMU allows multiple probes per event type. When creating a system that switches between CPU models that share the same PMU, PMU events for all of the CPU models can be registered with the PMU. Kudos to Matt Horsnell for the initial gem5 implementation of the PMU.
2014-04-29arm: use condition code registers for ARM ISACurtis Dunham
Analogous to ee049bf (for x86). Requires a bump of the checkpoint version and corresponding upgrader code to move the condition code register values to the new register file.
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
2014-01-24arch: Make all register index flattening constAndreas Hansson
This patch makes all the register index flattening methods const for all the ISAs. As part of this, readMiscRegNoEffect for ARM is also made const.
2013-10-15cpu: add a condition-code register classYasuko Eckert
Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
2013-02-19scons: Add warning for overloaded virtual functionsAndreas Hansson
Fix the ISA startup warnings
2013-01-12x86: Changes to decoder, corrects 9376Nilay Vaish
The changes made by the changeset 9376 were not quite correct. The patch made changes to the code which resulted in decoder not getting initialized correctly when the state was restored from a checkpoint. This patch adds a startup function to each ISA object. For x86, this function sets the required state in the decoder. For other ISAs, the function is empty right now.
2013-01-07arch: Move the ISA object to a separate sectionAndreas Sandberg
After making the ISA an independent SimObject, it is serialized automatically by the Python world. Previously, this just resulted in an empty ISA section. This patch moves the contents of the ISA to that section and removes the explicit ISA serialization from the thread contexts, which makes it behave like a normal SimObject during serialization. Note: This patch breaks checkpoint backwards compatibility! Use the cpt_upgrader.py utility to upgrade old checkpoints to the new format.
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
2010-11-08ARM: Add checkpointing supportAli Saidi
2010-08-23ARM: Clean up flattening for SPSR addingMin Kyu Jeong
2010-06-02ARM: Move the ISA "clear" function into isa.cc.Gabe Black
2010-06-02ARM: Some TLB bug fixes.Ali Saidi
2010-06-02ARM: Move Miscreg functions out of isa.hhAli Saidi
2010-06-02ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.Ali Saidi
2010-06-02ARM: Implement ARM CPU interruptsAli Saidi
2010-06-02ARM: Make various bits of the FP control registers read only.Gabe Black
2010-06-02ARM: Make MPIDR return 0 and ignore writes.Gabe Black
2010-06-02ARM: Set the value of the MVFR0 and MVFR1 registers.Gabe Black
2010-06-02ARM: Handle accesses to TLBTR.Gabe Black
2010-06-02ARM: Convert the CP15 registers from MPU to MMU.Gabe Black
2010-06-02ARM: Add some support for wfi/wfe/yield/etcAli Saidi
2010-06-02ARM: Add a traceflag to print cpsrAli Saidi
2010-06-02ARM: Ignore attempts to disable coprocessors that aren't implemented anyway.Gabe Black
2010-06-02ARM: Allow flattening into any mode.Gabe Black
2010-06-02ARM: Make the MPUIR register report that 1 unified data region is supported.Gabe Black
2010-06-02ARM: Ignore/warn when CSSELR or CCSIDR are accessed.Gabe Black
These registers provide information about the caches. Since we can't provide that information, these will be harmlessly inert.
2010-06-02ARM: Add support for the clidr register.Gabe Black
This register will always report 0 caches as implemented. It's not clear how to find out how many there really are when dealing with an arbitrary hierarchy.
2010-06-02ARM: Implement a stub of CPACR.Gabe Black
This register controls access to the coprocessors. This doesn't actually implement it, it allows writes which don't turn anything off. In other words, it allows the simulated program to ask for what it already has.
2010-06-02ARM: Actually write the value of sctlr in ISA.clear().Gabe Black
2010-06-02ARM: Implement a function to decode CP15 registers to MiscReg indices.Gabe Black
2010-06-02ARM: Track the current ISA mode using the PC.Gabe Black
2009-11-14ARM: Hook up the moded versions of the SPSR.Gabe Black
These registers can be accessed directly, or through MISCREG_SPSR which will act as whichever SPSR is appropriate for the current mode.
2009-11-10ARM: Implement fault classes.Gabe Black
Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-08ARM: Support forcing load/store multiple to use user registers.Gabe Black
2009-11-08ARM: Add in more bits for the mon mode.Gabe Black
2009-11-08ARM: Initialize processes in user mode.Gabe Black
I accidentally left in a change to test using int registers in system mode. This change reverts that.
2009-11-08ARM: Implement the shadow registers using register flattening.Gabe Black
2009-10-17ISA: Fix compilation.Gabe Black
2009-07-27ARM: Initialize the CPSR so that we're in user mode.Gabe Black
2009-07-09ARM: Fold the MiscRegFile all the way into the ISA object.Gabe Black
2009-07-08Registers: Collapse ARM and MIPS regfile directories.Gabe Black
--HG-- rename : src/arch/arm/regfile/misc_regfile.hh => src/arch/arm/misc_regfile.hh rename : src/arch/arm/regfile/regfile.cc => src/arch/arm/regfile.cc rename : src/arch/mips/regfile/misc_regfile.cc => src/arch/mips/misc_regfile.cc rename : src/arch/mips/regfile/misc_regfile.hh => src/arch/mips/misc_regfile.hh
2009-07-08Registers: Add an ISA object which replaces the MiscRegFile.Gabe Black
This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.