gem5 - gem5

Age	Commit message (Collapse)	Author
2010-06-02	ARM: Implement a function to decode CP15 registers to MiscReg indices.	Gabe Black

2010-06-02	ARM: Track the current ISA mode using the PC.	Gabe Black

2009-11-14	ARM: Hook up the moded versions of the SPSR.	Gabe Black
	These registers can be accessed directly, or through MISCREG_SPSR which will act as whichever SPSR is appropriate for the current mode.
2009-11-10	ARM: Implement fault classes.	Gabe Black
	Implement some fault classes using the curriously recurring template pattern, similar to SPARCs.
2009-11-08	ARM: Support forcing load/store multiple to use user registers.	Gabe Black

2009-11-08	ARM: Add in more bits for the mon mode.	Gabe Black

2009-11-08	ARM: Initialize processes in user mode.	Gabe Black
	I accidentally left in a change to test using int registers in system mode. This change reverts that.
2009-11-08	ARM: Implement the shadow registers using register flattening.	Gabe Black

2009-10-17	ISA: Fix compilation.	Gabe Black

2009-07-27	ARM: Initialize the CPSR so that we're in user mode.	Gabe Black

2009-07-09	ARM: Fold the MiscRegFile all the way into the ISA object.	Gabe Black

2009-07-08	Registers: Collapse ARM and MIPS regfile directories.	Gabe Black
	--HG-- rename : src/arch/arm/regfile/misc_regfile.hh => src/arch/arm/misc_regfile.hh rename : src/arch/arm/regfile/regfile.cc => src/arch/arm/regfile.cc rename : src/arch/mips/regfile/misc_regfile.cc => src/arch/mips/misc_regfile.cc rename : src/arch/mips/regfile/misc_regfile.hh => src/arch/mips/misc_regfile.hh
2009-07-08	Registers: Add an ISA object which replaces the MiscRegFile.	Gabe Black
	This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.