| Age | Commit message (Expand) | Author |
|---|
| 2019-09-06 | arch-arm: Add explicit AArch64 MiscReg banking | Giacomo Travaglini |
| 2019-08-07 | arch-arm: adding register control flags enabling LSE implementation | Jordi Vaquero |
| 2019-08-05 | arch-arm: Implement ARMv8.1-PAN, Privileged access never | Giacomo Travaglini |
| 2019-05-23 | arch-arm: Expose haveGicv3CPUInterface to the ISA interface | Giacomo Travaglini |
| 2019-03-14 | arch-arm,cpu: Add initial support for Arm SVE | Giacomo Gabrielli |
| 2019-01-30 | arch,cpu: Add vector predicate registers | Giacomo Gabrielli |
| 2019-01-25 | cpu, arch, arch-arm: Wire unused VecElem code in the O3 model | Giacomo Travaglini |
| 2019-01-22 | arch: cpu: Stop passing around misc registers by reference. | Gabe Black |
| 2019-01-22 | arm: Get rid of some register type definitions. | Gabe Black |
| 2019-01-15 | arch-arm: Fix usage of RegId constructor for VecElem | Giacomo Travaglini |
| 2019-01-10 | dev-arm: Add a GICv3 model | Jairo Balart |
| 2018-11-07 | arch-arm: Implement AArch32 RVBAR | Giacomo Travaglini |
| 2018-11-07 | arch-arm: Refactor ISA::clear by adding a ISA::clear32 method | Giacomo Travaglini |
| 2018-10-09 | arch-arm: Add have_crypto System parameter | Giacomo Travaglini |
| 2018-10-01 | arch-arm: Init AArch64 ID registers in SE mode | Giacomo Travaglini |
| 2018-09-13 | Fix SConstruct for asan build | Earl Ou |
| 2018-09-10 | arm: Add support for tracking TCs in ISA devices | Andreas Sandberg |
| 2018-05-29 | arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP | Giacomo Travaglini |
| 2018-04-18 | arch-arm: Adding MiscReg Priv (EL1) global flag | Giacomo Travaglini |
| 2018-03-23 | arch-arm: Distinguish IS TLBI from non-IS | Giacomo Travaglini |
| 2018-03-23 | arch-arm: Created function for TLB ASID Invalidation | Giacomo Travaglini |
| 2018-03-12 | arch-arm: Adding IPA-Based Invalidating instructions | Giacomo Travaglini |
| 2018-02-16 | arch-arm: Arch regs and pseudo regs distinction | Giacomo Travaglini |
| 2018-01-29 | arch-arm: understandably initialize register permissions | Curtis Dunham |
| 2018-01-29 | arm: extend MiscReg metadata structures | Curtis Dunham |
| 2018-01-29 | arch-arm: understandably initialize register mappings | Curtis Dunham |
| 2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Simplify the rename interface and use RegId | Rekai Gonzalez-Alberquilla |
| 2016-12-19 | arm: miscreg refactoring | Curtis Dunham |
| 2016-12-19 | arm: update AArch{64,32} register mappings | Curtis Dunham |
| 2016-08-02 | arm: enable EL2 support | Curtis Dunham |
| 2015-10-09 | isa: Add parameter to pick different decoder inside ISA | Rekai Gonzalez Alberquilla |
| 2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
| 2015-07-26 | cpu: implements vector registers | Nilay Vaish |
| 2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
| 2015-05-23 | dev, arm: Refactor and clean up the generic timer model | Andreas Sandberg |
| 2015-05-05 | arm: Remove unnecessary boot uncachability | Andreas Hansson |
| 2015-03-02 | arm: Don't truncate 16-bit ASIDs to 8 bits | Andreas Sandberg |
| 2014-10-29 | arm: Fix multi-system AArch64 boot w/caches. | Ali Saidi |
| 2014-10-16 | arm: Add a model of an ARM PMUv3 | Andreas Sandberg |
| 2014-04-29 | arm: use condition code registers for ARM ISA | Curtis Dunham |
| 2014-01-24 | arm: Add support for ARMv8 (AArch64 & AArch32) | ARM gem5 Developers |
| 2014-01-24 | arch: Make all register index flattening const | Andreas Hansson |
| 2013-10-15 | cpu: add a condition-code register class | Yasuko Eckert |
| 2013-02-19 | scons: Add warning for overloaded virtual functions | Andreas Hansson |
| 2013-01-12 | x86: Changes to decoder, corrects 9376 | Nilay Vaish |
| 2013-01-07 | arch: Move the ISA object to a separate section | Andreas Sandberg |
| 2013-01-07 | arch: Make the ISA class inherit from SimObject | Andreas Sandberg |
| 2011-04-15 | trace: reimplement the DTRACE function so it doesn't use a vector | Nathan Binkert |
| 2010-11-08 | ARM: Add checkpointing support | Ali Saidi |
