summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/bitfields.isa
AgeCommit message (Collapse)Author
2018-06-14arch-arm: Add Illegal Execution flag to PCStateGiacomo Travaglini
This patch moves the detection of the Illegal Execution flag (PSTATE.IL) from the tlb translation stage (fetch) to the decoding stage. This is done by adding the illegalExecution field to the PCState. Change-Id: I9c1c4e9c6bd5ded905c1d56b3034e4e9322582fa Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10813 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2016-02-06style: remove trailing whitespaceSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-white -a'.
2014-12-23arm: Raise an alignment fault if a PC has illegal alignmentAndreas Sandberg
We currently don't handle unaligned PCs correctly. There is one check for unaligned PCs in the TLB when running in aarch64 mode, but this check does not cover cases where the CPU does not do a TLB lookup when decoding an instruction (e.g., a branch stays within the same cache line). Additionally, the Decoder class sometimes throws an assertion for unaligned PCs which breaks speculation. This changeset introduces a decoder fault bit field in the ExtMachInst structure. This field can be used to signal a decoder failure. If set, the decoder generates an internal gem5fault instruction instead of a normal instruction. This instruction in turns either panics (fault type PANIC), returns an PCAlignmentFault (fault type UNALIGNED, aarch64) or PrefetchAbort (fault type UNALIGNED, aarch32). The patch causes minor changes to the realview64 regressions, and a stats bump will follow.
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
2010-06-02ARM: Rearrange the load/store double/exclusive, table branch thumb decoding.Gabe Black
2010-06-02ARM: Hook the new multiply instructions into all the decoders.Gabe Black
2010-06-02ARM: Make 32 bit thumb use the new, external load instructions.Gabe Black
2010-06-02ARM: Flesh out the 32 bit thumb store single instructions.Gabe Black
2010-06-02ARM: Flesh out 32 bit thumb load word decoding.Gabe Black
2010-06-02ARM: Add bitfields for 32 bit thumb.Gabe Black
2010-06-02ARM: Decode VFP instructions.Gabe Black
2010-06-02ARM: Add thumb bitfields to the ExtMachInst and the isa definition.Gabe Black
2010-06-02ARM: Add a thumb bit bitfield.Gabe Black
2009-11-17ARM: Begin implementing CP15Ali Saidi
2009-11-14ARM: Add a bitfield to indicate if an immediate should be used.Gabe Black
2009-11-14ARM: Move around decoder to properly decode CP15Ali Saidi
2009-11-10ARM: Fix some bugs in the ISA desc and fill out some instructions.Gabe Black
2009-07-01ARM: Get rid of some bitfields that aren't used. A few may need to be readded.Gabe Black
2009-07-01ARM: Decode some media instructions. These are untested.Gabe Black
2009-07-01ARM: Use the new DataOp format to simplify the decoder.Gabe Black
2009-07-01ARM: Add in some new artificial fields that make decoding a little easier.Gabe Black
2009-06-21ARM: Make inst bitfields accessible outside of the isa desc.Gabe Black
2009-06-21ARM: Get rid of unnecessary Re operand.Gabe Black
2009-04-05arm: add ARM support to M5Stephen Hines