Age | Commit message (Collapse) | Author | |
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2018-02-20 | arch-arm: Add AArch32 HLT Semihosting interface | Giacomo Travaglini | |
AArch32 HLT instruction is now able to issue Arm Semihosting commands as the AArch64 counterpart in either Arm and Thumb mode. Change-Id: I77da73d2e6a9288c704a5f646f4447022517ceb6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8372 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> | |||
2017-11-15 | arm: Add support for armv8 CRC32 instructions | Giacomo Travaglini | |
This patch introduces the ARM A32/T32/A64 CRC Instructions, which are mandatory since ARMv8.1. The UNPREDICTABLE behaviours are implemented as follows: 1) CRC32(C)X (64 bit) instructions are decoded as Undefined in Aarch32 2) The instructions support predication in Aarch32 3) Using R15(PC) as source/dest operand is permitted in Aarch32 Change-Id: Iaf29b05874e1370c7615da79a07f111ded17b6cc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5521 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> | |||
2014-12-23 | arm: Raise an alignment fault if a PC has illegal alignment | Andreas Sandberg | |
We currently don't handle unaligned PCs correctly. There is one check for unaligned PCs in the TLB when running in aarch64 mode, but this check does not cover cases where the CPU does not do a TLB lookup when decoding an instruction (e.g., a branch stays within the same cache line). Additionally, the Decoder class sometimes throws an assertion for unaligned PCs which breaks speculation. This changeset introduces a decoder fault bit field in the ExtMachInst structure. This field can be used to signal a decoder failure. If set, the decoder generates an internal gem5fault instruction instead of a normal instruction. This instruction in turns either panics (fault type PANIC), returns an PCAlignmentFault (fault type UNALIGNED, aarch64) or PrefetchAbort (fault type UNALIGNED, aarch32). The patch causes minor changes to the realview64 regressions, and a stats bump will follow. | |||
2014-01-24 | arm: Add support for ARMv8 (AArch64 & AArch32) | ARM gem5 Developers | |
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black | |||
2012-03-01 | ARM: Add limited CP14 support. | Matt Horsnell | |
New kernels attempt to read CP14 what debug architecture is available. These changes add the debug registers and return that none is currently available. | |||
2010-11-08 | ARM: Add support for M5 ops in the ARM ISA | Ali Saidi | |
2010-08-25 | ARM: Implement all ARM SIMD instructions. | Gabe Black | |
2010-06-02 | ARM: Decode the neon instruction space. | Gabe Black | |
2010-06-02 | ARM: Move some case values out of ##included files. | Gabe Black | |
This will help keep the high level decode together and not have it spread into the subordinate decode stuff. The ##include lines still need to be on a line by themselves, though. | |||
2010-06-02 | ARM: Move some miscellaneous instructions out of the decoder to share with ↵ | Gabe Black | |
thumb. | |||
2010-06-02 | ARM: Get rid of some of the old FP implementation. | Gabe Black | |
2010-06-02 | ARM: Add BKPT instruction | Ali Saidi | |
--HG-- rename : src/arch/arm/isa/formats/unknown.isa => src/arch/arm/isa/formats/breakpoint.isa | |||
2010-06-02 | ARM: Implement ARM CPU interrupts | Ali Saidi | |
2010-06-02 | ARM: Move the VFP data operation decode into a function. | Gabe Black | |
2010-06-02 | ARM: Add some support for wfi/wfe/yield/etc | Ali Saidi | |
2010-06-02 | ARM: BXJ should be BX when there is no J support | Ali Saidi | |
2010-06-02 | ARM: Fix up thumb decoding of coproc instructions. | Gabe Black | |
2010-06-02 | ARM: Clean up some redundancy and fault behavior for unimplemented thumb ↵ | Gabe Black | |
MCR, MRC. | |||
2010-06-02 | ARM: Make VFP load/store and 64 bit move decode correspond with CP10 and CP11. | Gabe Black | |
2010-06-02 | ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) ↵ | Gabe Black | |
registers. | |||
2010-06-02 | ARM: Decode the RFE instruction. | Gabe Black | |
2010-06-02 | ARM: When an instruction is intentionally undefined, fault on it. | Gabe Black | |
2010-06-02 | ARM: Decode the thumb32 load byte/memory hint instructions. | Gabe Black | |
2010-06-02 | ARM: Decode the load halfword, memory hints instructions for 32 bit Thumb. | Gabe Black | |
2010-06-02 | ARM: Replace the ARM decode of CP15 MCR and MRC instructions. | Gabe Black | |
2010-06-02 | ARM: Decode the thumb versions of the mcr and mrc instructions. | Gabe Black | |
2010-06-02 | ARM: Decode miscellaneous arm mode media instructions. | Gabe Black | |
2010-06-02 | ARM: Decode the clz instruction. | Gabe Black | |
2010-06-02 | ARM: Rearrange the load/store double/exclusive, table branch thumb decoding. | Gabe Black | |
2010-06-02 | ARM: Decode the usad8 and usada8 instructions. | Gabe Black | |
2010-06-02 | ARM: Decode 32 bit thumb data processing register instructions. | Gabe Black | |
2010-06-02 | ARM: Pull decoding of ARM pack, unpack, saturate and reverse instructions ↵ | Gabe Black | |
into a format. | |||
2010-06-02 | ARM: Decode the swp and swpb instructions. | Gabe Black | |
2010-06-02 | ARM: Replace the versions of MRS and MSR in the ARM decoder with the new ones. | Gabe Black | |
2010-06-02 | ARM: Implement SVC (was SWI) outside of the decoder. | Gabe Black | |
2010-06-02 | ARM: Trigger system calls from the SupervisorCall invoke method. | Gabe Black | |
This simplifies the decoder slightly, and makes the system call mechanism very slightly more realistic. | |||
2010-06-02 | ARM: Decode the scalar saturating add/subtract instructions. | Gabe Black | |
2010-06-02 | ARM: Decode the parallel add and subtract instructions. | Gabe Black | |
2010-06-02 | ARM: Decode unconditional ARM instructions. | Gabe Black | |
2010-06-02 | ARM: Define the VFP load/store multiple instructions. | Gabe Black | |
2010-06-02 | ARM: Hook the new multiply instructions into all the decoders. | Gabe Black | |
2010-06-02 | ARM: Decode plain binary immediate thumb data processing instructions. | Gabe Black | |
2010-06-02 | ARM: Hook the new branch instructions into the 32 bit thumb decoder. | Gabe Black | |
2010-06-02 | ARM: Hook the new branch instructions into the 16 bit thumb decoder. | Gabe Black | |
2010-06-02 | ARM: Hook the new branch instructions into the ARM decoder. | Gabe Black | |
2010-06-02 | ARM: Implement branch instructions external to the decoder. | Gabe Black | |
2010-06-02 | ARM: Hook the external data processing instructions into the Thumb decoder. | Gabe Black | |
2010-06-02 | ARM: Hook the new external data processing instructions to the ARM decoder. | Gabe Black | |
2010-06-02 | ARM: Hook up 32 bit thumb load/store multiple. | Gabe Black | |
2010-06-02 | ARM: Hook up 16 bit thumb load/store multiple. | Gabe Black | |