gem5 - gem5

Age	Commit message (Expand)	Author
2018-10-26	arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL	Giacomo Travaglini
2018-10-19	arm: treat aarch64 hints as NOPs instead of panic	Ciro Santilli
2018-10-19	arm: update hint instruction decoding to match ARMv8.5	Ciro Santilli
2018-10-09	arch-arm: AArch64 Crypto AES	Giacomo Travaglini
2018-10-09	arch-arm: AArch64 Crypto SHA	Giacomo Travaglini
2018-10-02	arch-arm: Add FP16 support introduced by Armv8.2-A	Edmund Grimley Evans
2018-08-10	arm: Add support for RCpc load-acquire instructions (ARMv8.3)	Giacomo Gabrielli
2018-05-29	arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP	Giacomo Travaglini
2018-04-19	arch-arm: Change disassemble when MSR to UNKNOWN register	Giacomo Travaglini
2018-03-20	arch, arm: Fix implicit-fallthrough GCC warnings	Chun-Chen Hsu
2018-03-15	arm: Fix implicit-fallthrough warnings when building with gcc-7+	Siddhesh Poyarekar
2018-02-20	arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly	Giacomo Travaglini
2018-02-19	arch-arm: Add aarch64 semihosting support	Andreas Sandberg
2018-02-16	arch-arm: Decode Brk64 instructions	Andreas Sandberg
2017-12-05	arm: Add support for the dc {civac, cvac, cvau, ivac} instr	Nikos Nikoleris
2017-11-21	arch-arm: Fix MSR/MRS disassemble	Giacomo Travaglini
2017-11-15	arm: Add support for armv8 CRC32 instructions	Giacomo Travaglini
2017-08-01	arch-arm: Use named constants for m5op instructions	Andreas Sandberg
2016-09-15	arm: Add m5_fail support for aarch64	Ricardo Alves
2016-08-02	arm: Add AArch64 hypervisor call instruction 'hvc'	Dylan Johnson
2015-10-09	isa: Add parameter to pick different decoder inside ISA	Rekai Gonzalez Alberquilla
2014-10-29	arm: Mark some miscregs (timer counter) registers at unverifiable.	Ali Saidi
2014-09-03	arm: ISA X31 destination register fix	Andrew Bardsley
2014-04-23	arm: Don't use a stack allocated mnemonic	Mitchell Hayenga
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers