Age | Commit message (Collapse) | Author | |
---|---|---|---|
2017-11-13 | arch-arm: Corrected encoding for T32 HVC instruction | Giacomo Travaglini | |
This patch corrects the encoding of the HVC (Hypervisor Call) for the T32 instruction set. Change-Id: I6f77eaf5c586697e9ccd588419c61e6d90c6c7bf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chuan Zhu <chuan.zhu@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5541 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> | |||
2014-01-24 | arm: Add support for ARMv8 (AArch64 & AArch32) | ARM gem5 Developers | |
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black | |||
2012-03-21 | ARM: Clean up condCodes in IT blocks. | Ali Saidi | |
2010-08-23 | ARM: Implement DBG instruction that doesn't do much for now. | Gene Wu | |
2010-08-23 | ARM: Implement DSB, DMB, ISB | Gene Wu | |
2010-08-23 | ARM: Implement CLREX | Gene Wu | |
2010-08-23 | ARM: BX instruction can be contitional if last instruction in a IT block | Gene Wu | |
Branches are allowed to be the last instuction in an IT block. Before it was assumed that they could not. So Branches in thumb2 were Uncond. | |||
2010-06-02 | ARM: Hook the misc instructions into the thumb decoder. | Gabe Black | |
2010-06-02 | ARM: BXJ should be BX when there is no J support | Ali Saidi | |
2010-06-02 | ARM: Decode the CPS instruction. | Gabe Black | |
2010-06-02 | ARM: Make sure some undefined thumb32 instructions fault. | Gabe Black | |
2010-06-02 | ARM: Decode the enterx and leavex instructions. | Gabe Black | |
2010-06-02 | ARM: When an instruction is intentionally undefined, fault on it. | Gabe Black | |
2010-06-02 | ARM: Decode the clz instruction. | Gabe Black | |
2010-06-02 | ARM: Decode the nop instruction. | Gabe Black | |
2010-06-02 | ARM: Decode MRS and MSR for thumb. | Gabe Black | |
2010-06-02 | ARM: Hook SVC into the thumb decoder. | Gabe Black | |
2010-06-02 | ARM: Add support for "SUBS PC, LR and related instructions". | Gabe Black | |
2010-06-02 | ARM: Hook the new branch instructions into the 32 bit thumb decoder. | Gabe Black | |
2010-06-02 | ARM: Hook the new branch instructions into the 16 bit thumb decoder. | Gabe Black | |
2010-06-02 | ARM: Eliminate the old style branch instructions. | Gabe Black | |
2010-06-02 | ARM: Hook the new branch instructions into the ARM decoder. | Gabe Black | |
2010-06-02 | ARM: Get rid of the unused Jump format. | Gabe Black | |
2009-11-08 | ARM: Split the condition codes out of the CPSR. | Gabe Black | |
This allows those bits to be renamed while allowing the other fields to control the behavior of the processor. | |||
2009-06-24 | ARM: Link register is trashed by non-executed branch and link operations. | Jack Whitman | |
2009-06-21 | ARM: Simplify the ISA desc by pulling some classes out of it. | Gabe Black | |
2009-06-21 | ARM: Make the isa parser aware that CPSR is being used. | Gabe Black | |
2009-06-21 | ARM: Pull some static code out of the isa desc and create miscregs.hh. | Gabe Black | |
2009-04-05 | arm: add ARM support to M5 | Stephen Hines | |