gem5 - gem5

Age	Commit message (Expand)	Author
2010-08-23	ARM: Implement DBG instruction that doesn't do much for now.	Gene Wu
2010-08-23	ARM: Implement DSB, DMB, ISB	Gene Wu
2010-08-23	ARM: Implement CLREX	Gene Wu
2010-08-23	ARM: BX instruction can be contitional if last instruction in a IT block	Gene Wu
2010-06-02	ARM: Hook the misc instructions into the thumb decoder.	Gabe Black
2010-06-02	ARM: BXJ should be BX when there is no J support	Ali Saidi
2010-06-02	ARM: Decode the CPS instruction.	Gabe Black
2010-06-02	ARM: Make sure some undefined thumb32 instructions fault.	Gabe Black
2010-06-02	ARM: Decode the enterx and leavex instructions.	Gabe Black
2010-06-02	ARM: When an instruction is intentionally undefined, fault on it.	Gabe Black
2010-06-02	ARM: Decode the clz instruction.	Gabe Black
2010-06-02	ARM: Decode the nop instruction.	Gabe Black
2010-06-02	ARM: Decode MRS and MSR for thumb.	Gabe Black
2010-06-02	ARM: Hook SVC into the thumb decoder.	Gabe Black
2010-06-02	ARM: Add support for "SUBS PC, LR and related instructions".	Gabe Black
2010-06-02	ARM: Hook the new branch instructions into the 32 bit thumb decoder.	Gabe Black
2010-06-02	ARM: Hook the new branch instructions into the 16 bit thumb decoder.	Gabe Black
2010-06-02	ARM: Eliminate the old style branch instructions.	Gabe Black
2010-06-02	ARM: Hook the new branch instructions into the ARM decoder.	Gabe Black
2010-06-02	ARM: Get rid of the unused Jump format.	Gabe Black
2009-11-08	ARM: Split the condition codes out of the CPSR.	Gabe Black
2009-06-24	ARM: Link register is trashed by non-executed branch and link operations.	Jack Whitman
2009-06-21	ARM: Simplify the ISA desc by pulling some classes out of it.	Gabe Black
2009-06-21	ARM: Make the isa parser aware that CPSR is being used.	Gabe Black
2009-06-21	ARM: Pull some static code out of the isa desc and create miscregs.hh.	Gabe Black
2009-04-05	arm: add ARM support to M5	Stephen Hines