| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2011-02-23 | ARM: Do something for ISB, DSB, DMB | Ali Saidi | |
| 2011-02-23 | ARM: Adds dummy support for a L2 latency miscreg. | Ali Saidi | |
| 2011-01-18 | ARM: The ARM decoder should not panic when decoding undefined holes is arch. | Matt Horsnell | |
| This can abort simulations when the fetch unit runs ahead and speculatively decodes instructions that are off the execution path. | |||
| 2010-11-15 | ARM: Return an FailUnimp instruction when an unimplemented CP15 register is ↵ | Ali Saidi | |
| accessed. Just panicing in readMiscReg() doesn't work because a speculative access in the o3 model can end the simulation. | |||
| 2010-08-25 | ARM: Adding a bogus fault that does nothing. | Min Kyu Jeong | |
| This fault can used to flush the pipe, not including the faulting instruction. The particular case I needed this was for a self-modifying code. It needed to drain the store queue and force the following instruction to refetch from icache. DCCMVAC cp15 mcr instruction is modified to raise this fault. | |||
| 2010-08-23 | ARM: Implement some more misc registers | Ali Saidi | |
| 2010-06-02 | ARM: Implement a version of mcr and mrc that works in user mode. | Gabe Black | |
| 2010-06-02 | ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements. | Ali Saidi | |
| 2010-06-02 | ARM: Ignore reads and writes to DCIMVAC. | Gabe Black | |
| 2010-06-02 | ARM: Move the CP15 decode block into a function. | Gabe Black | |
| 2010-06-02 | ARM: Warn/ignore when TLB maintenance operations are performed. | Gabe Black | |
| 2010-06-02 | ARM: Convert the CP15 registers from MPU to MMU. | Gabe Black | |
| 2010-06-02 | ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers. | Gabe Black | |
| 2010-06-02 | ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers. | Gabe Black | |
| 2010-06-02 | ARM: Ignore/warn access to the bpimva registers. | Gabe Black | |
| 2010-06-02 | ARM: Ignore/warn on accesses to the dccmvac register. | Gabe Black | |
| 2010-06-02 | ARM: Ignore/warn on accesses to icimvau. | Gabe Black | |
| 2010-06-02 | ARM: Ignore/warn on ICIALLUIS. | Gabe Black | |
| 2010-06-02 | ARM: Decode the unimplemented data barrier CP15 accesses. | Gabe Black | |
| These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory Barrier). | |||
| 2010-06-02 | ARM: Decode the unimplemented cp15 instruction barrier. | Gabe Black | |
| 2010-06-02 | ARM: Ignore accesses to DCCIMVAC. | Gabe Black | |
| 2010-06-02 | ARM: Warn about and ignore accesses to DCCISW. | Gabe Black | |
| This register is supposed to "Clean and invalidate data or unified cache line by set/way." Since there isn't a good way to do that, we'll just ignore these and warn about it. | |||
| 2010-06-02 | ARM: Decode the thumb versions of the mcr and mrc instructions. | Gabe Black | |
| 2010-06-02 | ARM: Replace the versions of MRS and MSR in the ARM decoder with the new ones. | Gabe Black | |
| 2010-06-02 | ARM: Implement SVC (was SWI) outside of the decoder. | Gabe Black | |
 |
index : gem5 | |
| gem5 |
| summaryrefslogtreecommitdiff |