| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2011-05-13 | ARM: Construct the predicate test register for more instruction programatically. | Ali Saidi | |
| If one of the condition codes isn't being used in the execution we should only read it if the instruction might be dependent on it. With the preeceding changes there are several more cases where we should dynamically pick instead of assuming as we did before. | |||
| 2011-05-13 | ARM: Further break up condition code into NZ, C, V bits. | Ali Saidi | |
| Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions. | |||
| 2011-05-13 | ARM: Break up condition codes into normal flags, saturation, and simd. | Ali Saidi | |
| This change splits out the condcodes from being one monolithic register into three blocks that are updated independently. This allows CPUs to not have to do RMW operations on the flags registers for instructions that don't write all flags. | |||
| 2010-06-02 | ARM: Decode to specialized conditional/unconditional versions of instructions. | Gabe Black | |
| This is to avoid condition code based dependences from effectively serializing instructions when the instruction doesn't actually use them. | |||
| 2010-06-02 | ARM: Get rid of obsoleted predicated inst formats, etc. | Gabe Black | |
| 2010-06-02 | ARM: Move the templates for predicated instructions into a separate file. | Gabe Black | |
| This allows the templates to all be available at the same time before any of the formats, etc. This breaks an artificial circular dependence. --HG-- rename : src/arch/arm/isa/formats/pred.isa => src/arch/arm/isa/templates/pred.isa | |||
| 2010-06-02 | ARM: Add a base class for 32 bit thumb data processing immediate instructions. | Gabe Black | |
| 2009-11-10 | ARM: Fix some bugs in the ISA desc and fill out some instructions. | Gabe Black | |
| 2009-11-08 | ARM: Split the condition codes out of the CPSR. | Gabe Black | |
| This allows those bits to be renamed while allowing the other fields to control the behavior of the processor. | |||
| 2009-07-29 | ARM: Mul and mla ignore the c and v flags, but we were setting them to 1. | Gabe Black | |
| 2009-07-01 | ARM: Make DataOps select from a set of ways to set the c and v flags. | Gabe Black | |
| 2009-07-01 | ARM: Add defaults for DataOp flag code. | Gabe Black | |
| 2009-07-01 | ARM: Get rid of the val2 variable. | Gabe Black | |
| 2009-07-01 | ARM: Centralize the declaration of resTemp. | Gabe Black | |
| 2009-07-01 | ARM: Add a DataImmOp format similar to DataOp. | Gabe Black | |
| 2009-07-01 | ARM: Add a DataOp format so data op definitions can be aggregated. | Gabe Black | |
| 2009-06-21 | ARM: Simplify the ISA desc by pulling some classes out of it. | Gabe Black | |
| 2009-06-21 | ARM: Make inst bitfields accessible outside of the isa desc. | Gabe Black | |
| 2009-06-21 | ARM: Get rid of unnecessary fp_enable_checks. | Gabe Black | |
| 2009-06-21 | ARM: Adjust simplify rotate_imm slightly. | Gabe Black | |
| 2009-06-21 | ARM: Make the isa parser aware that CPSR is being used. | Gabe Black | |
| 2009-06-21 | ARM: Pull some static code out of the isa desc and create miscregs.hh. | Gabe Black | |
| 2009-04-05 | arm: add ARM support to M5 | Stephen Hines | |
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