| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-06-22 | arch-arm: BadMode checking if corresponding EL is implemented | Giacomo Travaglini | |
| The old utility function called badMode was only checking if the mode passed as an argument was a recognized mode. It was not checking if the corresponding mode/EL was implemented. That function has been renamed to unknownMode and a new badMode has been introduced. This is used by the cpsrWriteByInstruction function. In this way any try to change the execution mode won't succeed if the mode hasn't been implemented. Change-Id: Ibfe385c5465b904acc0d2eb9647710891d72c9df Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11196 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> | |||
| 2014-01-24 | arm: Add support for ARMv8 (AArch64 & AArch32) | ARM gem5 Developers | |
| Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black | |||
| 2012-03-01 | ARM: Add limited CP14 support. | Matt Horsnell | |
| New kernels attempt to read CP14 what debug architecture is available. These changes add the debug registers and return that none is currently available. | |||
| 2010-08-23 | ARM: Implement DSB, DMB, ISB | Gene Wu | |
| 2010-08-23 | ARM: Implement CLREX | Gene Wu | |
| 2010-08-23 | ARM: BX instruction can be contitional if last instruction in a IT block | Gene Wu | |
| Branches are allowed to be the last instuction in an IT block. Before it was assumed that they could not. So Branches in thumb2 were Uncond. | |||
| 2010-07-15 | ARM: Make an SRS instruction with a bad mode cause an undefined instruction ↵ | Gabe Black | |
| fault. | |||
| 2010-06-02 | ARM: Decode the neon instruction space. | Gabe Black | |
| 2010-06-02 | ARM: Make sure undefined unconditional ARM instructions decode as such. | Gabe Black | |
| 2010-06-02 | ARM: Decode ARM unconditional MRC and MCR instructions. | Gabe Black | |
| 2010-06-02 | ARM: Decode the unconditional version of ARM fp instructions. | Gabe Black | |
| 2010-06-02 | ARM: Decode the CPS instruction. | Gabe Black | |
| 2010-06-02 | ARM: Decode the SRS instruction. | Gabe Black | |
| 2010-06-02 | ARM: Decode the setend instruction. | Gabe Black | |
| 2010-06-02 | ARM: Decode the RFE instruction. | Gabe Black | |
| 2010-06-02 | ARM: Decode the nop instruction. | Gabe Black | |
| 2010-06-02 | ARM: Implemented prefetch instructions/decoding (pli, pld, pldw). | Gabe Black | |
| 2010-06-02 | ARM: Decode unconditional ARM instructions. | Gabe Black | |
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