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path: root/src/arch/arm/isa/formats
AgeCommit message (Expand)Author
2017-12-05arm: Add support for the dc {civac, cvac, cvau, ivac} instrNikos Nikoleris
2017-12-05arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructionsNikos Nikoleris
2017-11-21arch-arm: Fix MSR/MRS disassembleGiacomo Travaglini
2017-11-15arm: Add support for armv8 CRC32 instructionsGiacomo Travaglini
2017-11-13arch-arm: Corrected encoding for T32 HVC instructionGiacomo Travaglini
2017-11-07alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates.Gabe Black
2017-11-02alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.Gabe Black
2017-08-01arch-arm: Use named constants for m5op instructionsAndreas Sandberg
2016-10-13isa,arm: Add missing AArch32 FP instructionsMitch Hayenga
2016-09-15arm: Add m5_fail support for aarch64Ricardo Alves
2016-08-02arm: Add AArch64 hypervisor call instruction 'hvc'Dylan Johnson
2016-08-02arm: change instruction classes to catch hyp trapsDylan Johnson
2016-02-06style: remove trailing whitespaceSteve Reinhardt
2015-10-09isa: Add parameter to pick different decoder inside ISARekai Gonzalez Alberquilla
2015-02-16arm: Merge ISA files with pseudo instructionsAndreas Sandberg
2014-12-23arm: Raise an alignment fault if a PC has illegal alignmentAndreas Sandberg
2014-10-29arm: Mark some miscregs (timer counter) registers at unverifiable.Ali Saidi
2014-10-16arch: Use shared_ptr for all FaultsAndreas Hansson
2014-10-01arm: More UBSan cleanups after additional full-system runsAndreas Hansson
2014-09-27arm: Fixed undefined behaviours identified by gccAndreas Hansson
2014-09-03arm: ISA X31 destination register fixAndrew Bardsley
2014-05-09arch: teach ISA parser how to split code across filesCurtis Dunham
2014-04-23arm: Don't use a stack allocated mnemonicMitchell Hayenga
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2013-05-14arm: Add support for the m5fail pseudo-opAndreas Sandberg
2013-02-19scons: Add warning for missing declarationsAndreas Hansson
2013-02-19scons: Fix up numerous warnings about name shadowingAndreas Hansson
2012-03-21ARM: Clean up condCodes in IT blocks.Ali Saidi
2012-03-01ARM: Add limited CP14 support.Matt Horsnell
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31util: implements "writefile" gem5 op to export file from guest to host filesy...Dam Sunwoo
2012-01-07Merge with main repository.Gabe Black
2011-11-02SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.Gabe Black
2011-10-31GCC: Get everything working with gcc 4.6.1.Gabe Black
2011-09-13CP15 c15: enable execution with accesses to c15 registersChander Sudanthi
2011-08-19ARM: Add support for DIV/SDIV instructions.Ali Saidi
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-05-13ARM: Construct the predicate test register for more instruction programatically.Ali Saidi
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
2011-05-04ARM: Fix small bug with vcvt instructionAli Saidi
2011-03-17ARM: Fix small bug with VLDM/VSTM instructions.Ali Saidi
2011-02-23ARM: Do something for ISB, DSB, DMBAli Saidi
2011-02-23ARM: Adds dummy support for a L2 latency miscreg.Ali Saidi
2011-01-18ARM: The ARM decoder should not panic when decoding undefined holes is arch.Matt Horsnell
2010-11-15ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a...Ali Saidi
2010-11-08ARM: Add support for M5 ops in the ARM ISAAli Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-08-25ARM: Adding a bogus fault that does nothing.Min Kyu Jeong
2010-08-25ARM: Seperate out the renamable bits in the FPSCR.Gabe Black