| Age | Commit message (Expand) | Author |
|---|
| 2017-12-05 | arm: Add support for the dc {civac, cvac, cvau, ivac} instr | Nikos Nikoleris |
| 2017-12-05 | arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructions | Nikos Nikoleris |
| 2017-11-21 | arch-arm: Fix MSR/MRS disassemble | Giacomo Travaglini |
| 2017-11-15 | arm: Add support for armv8 CRC32 instructions | Giacomo Travaglini |
| 2017-11-13 | arch-arm: Corrected encoding for T32 HVC instruction | Giacomo Travaglini |
| 2017-11-07 | alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates. | Gabe Black |
| 2017-11-02 | alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts. | Gabe Black |
| 2017-08-01 | arch-arm: Use named constants for m5op instructions | Andreas Sandberg |
| 2016-10-13 | isa,arm: Add missing AArch32 FP instructions | Mitch Hayenga |
| 2016-09-15 | arm: Add m5_fail support for aarch64 | Ricardo Alves |
| 2016-08-02 | arm: Add AArch64 hypervisor call instruction 'hvc' | Dylan Johnson |
| 2016-08-02 | arm: change instruction classes to catch hyp traps | Dylan Johnson |
| 2016-02-06 | style: remove trailing whitespace | Steve Reinhardt |
| 2015-10-09 | isa: Add parameter to pick different decoder inside ISA | Rekai Gonzalez Alberquilla |
| 2015-02-16 | arm: Merge ISA files with pseudo instructions | Andreas Sandberg |
| 2014-12-23 | arm: Raise an alignment fault if a PC has illegal alignment | Andreas Sandberg |
| 2014-10-29 | arm: Mark some miscregs (timer counter) registers at unverifiable. | Ali Saidi |
| 2014-10-16 | arch: Use shared_ptr for all Faults | Andreas Hansson |
| 2014-10-01 | arm: More UBSan cleanups after additional full-system runs | Andreas Hansson |
| 2014-09-27 | arm: Fixed undefined behaviours identified by gcc | Andreas Hansson |
| 2014-09-03 | arm: ISA X31 destination register fix | Andrew Bardsley |
| 2014-05-09 | arch: teach ISA parser how to split code across files | Curtis Dunham |
| 2014-04-23 | arm: Don't use a stack allocated mnemonic | Mitchell Hayenga |
| 2014-01-24 | arm: Add support for ARMv8 (AArch64 & AArch32) | ARM gem5 Developers |
| 2013-05-14 | arm: Add support for the m5fail pseudo-op | Andreas Sandberg |
| 2013-02-19 | scons: Add warning for missing declarations | Andreas Hansson |
| 2013-02-19 | scons: Fix up numerous warnings about name shadowing | Andreas Hansson |
| 2012-03-21 | ARM: Clean up condCodes in IT blocks. | Ali Saidi |
| 2012-03-01 | ARM: Add limited CP14 support. | Matt Horsnell |
| 2012-01-31 | Merge with head, hopefully the last time for this batch. | Gabe Black |
| 2012-01-31 | util: implements "writefile" gem5 op to export file from guest to host filesy... | Dam Sunwoo |
| 2012-01-07 | Merge with main repository. | Gabe Black |
| 2011-11-02 | SE/FS: Get rid of FULL_SYSTEM in the ARM ISA. | Gabe Black |
| 2011-10-31 | GCC: Get everything working with gcc 4.6.1. | Gabe Black |
| 2011-09-13 | CP15 c15: enable execution with accesses to c15 registers | Chander Sudanthi |
| 2011-08-19 | ARM: Add support for DIV/SDIV instructions. | Ali Saidi |
| 2011-06-17 | ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA. | Gedare Bloom |
| 2011-05-13 | ARM: Construct the predicate test register for more instruction programatically. | Ali Saidi |
| 2011-05-13 | ARM: Further break up condition code into NZ, C, V bits. | Ali Saidi |
| 2011-05-13 | ARM: Break up condition codes into normal flags, saturation, and simd. | Ali Saidi |
| 2011-05-04 | ARM: Fix small bug with vcvt instruction | Ali Saidi |
| 2011-03-17 | ARM: Fix small bug with VLDM/VSTM instructions. | Ali Saidi |
| 2011-02-23 | ARM: Do something for ISB, DSB, DMB | Ali Saidi |
| 2011-02-23 | ARM: Adds dummy support for a L2 latency miscreg. | Ali Saidi |
| 2011-01-18 | ARM: The ARM decoder should not panic when decoding undefined holes is arch. | Matt Horsnell |
| 2010-11-15 | ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a... | Ali Saidi |
| 2010-11-08 | ARM: Add support for M5 ops in the ARM ISA | Ali Saidi |
| 2010-10-31 | ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. | Gabe Black |
| 2010-08-25 | ARM: Adding a bogus fault that does nothing. | Min Kyu Jeong |
| 2010-08-25 | ARM: Seperate out the renamable bits in the FPSCR. | Gabe Black |
