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path: root/src/arch/arm/isa/formats
AgeCommit message (Expand)Author
2014-09-03arm: ISA X31 destination register fixAndrew Bardsley
2014-05-09arch: teach ISA parser how to split code across filesCurtis Dunham
2014-04-23arm: Don't use a stack allocated mnemonicMitchell Hayenga
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2013-05-14arm: Add support for the m5fail pseudo-opAndreas Sandberg
2013-02-19scons: Add warning for missing declarationsAndreas Hansson
2013-02-19scons: Fix up numerous warnings about name shadowingAndreas Hansson
2012-03-21ARM: Clean up condCodes in IT blocks.Ali Saidi
2012-03-01ARM: Add limited CP14 support.Matt Horsnell
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31util: implements "writefile" gem5 op to export file from guest to host filesy...Dam Sunwoo
2012-01-07Merge with main repository.Gabe Black
2011-11-02SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.Gabe Black
2011-10-31GCC: Get everything working with gcc 4.6.1.Gabe Black
2011-09-13CP15 c15: enable execution with accesses to c15 registersChander Sudanthi
2011-08-19ARM: Add support for DIV/SDIV instructions.Ali Saidi
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-05-13ARM: Construct the predicate test register for more instruction programatically.Ali Saidi
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
2011-05-04ARM: Fix small bug with vcvt instructionAli Saidi
2011-03-17ARM: Fix small bug with VLDM/VSTM instructions.Ali Saidi
2011-02-23ARM: Do something for ISB, DSB, DMBAli Saidi
2011-02-23ARM: Adds dummy support for a L2 latency miscreg.Ali Saidi
2011-01-18ARM: The ARM decoder should not panic when decoding undefined holes is arch.Matt Horsnell
2010-11-15ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a...Ali Saidi
2010-11-08ARM: Add support for M5 ops in the ARM ISAAli Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-08-25ARM: Adding a bogus fault that does nothing.Min Kyu Jeong
2010-08-25ARM: Seperate out the renamable bits in the FPSCR.Gabe Black
2010-08-25ARM: Implement all ARM SIMD instructions.Gabe Black
2010-08-23ARM: Implement DBG instruction that doesn't do much for now.Gene Wu
2010-08-23ARM: Implement DSB, DMB, ISBGene Wu
2010-08-23ARM: Implement CLREXGene Wu
2010-08-23ARM: BX instruction can be contitional if last instruction in a IT blockGene Wu
2010-08-23ARM: Decode neon memory instructions.Ali Saidi
2010-08-23ARM: Implement some more misc registersAli Saidi
2010-07-15ARM: Make an SRS instruction with a bad mode cause an undefined instruction f...Gabe Black
2010-06-02ARM: Decode the neon instruction space.Gabe Black
2010-06-02ARM: Combine some redundant cases in one of the data decode functions.Gabe Black
2010-06-02ARM: Get rid of the binary dumping function in utility.hh.Gabe Black
2010-06-02ARM: Decode to specialized conditional/unconditional versions of instructions.Gabe Black
2010-06-02ARM: Make sure undefined unconditional ARM instructions decode as such.Gabe Black
2010-06-02ARM: Implement a version of mcr and mrc that works in user mode.Gabe Black
2010-06-02ARM: Hook the misc instructions into the thumb decoder.Gabe Black
2010-06-02ARM: Move some miscellaneous instructions out of the decoder to share with th...Gabe Black
2010-06-02ARM: Treat LDRD in ARM with an odd index as an undefined instruction.Gabe Black
2010-06-02ARM: Detect a bad offset field for the VFP Ldm/Stm instructions in the decoder.Gabe Black
2010-06-02ARM: Implement the bkpt instruction.Gabe Black
2010-06-02ARM: Make undefined instructions obey predication.Gabe Black