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path: root/src/arch/arm/isa/formats
AgeCommit message (Expand)Author
2010-06-02ARM: Implement conversion to/from half precision.Gabe Black
2010-06-02ARM: Even though writes to MVFR0/1 should be unpredictable, we need to make t...Gabe Black
2010-06-02ARM: Implement the version of VMRS that writes to the APSR.Gabe Black
2010-06-02ARM: Ignore reads and writes to DCIMVAC.Gabe Black
2010-06-02ARM: Implement the VCMPE instruction.Gabe Black
2010-06-02ARM: Implement the version of VCVT float to int that rounds towards zero.Gabe Black
2010-06-02ARM: Implement the floating/fixed point VCVT instructions.Gabe Black
2010-06-02ARM: Implement the VFP version of VCMP.Gabe Black
2010-06-02ARM: Add support for VFP vector mode.Gabe Black
2010-06-02ARM: Implement VCVT between double and single width FP.Gabe Black
2010-06-02ARM: Implement vcvt between int and fp. Ignore rounding.Gabe Black
2010-06-02ARM: Consolidate the VFP register index computation code.Gabe Black
2010-06-02ARM: Implement the VFP negated multiplies.Gabe Black
2010-06-02ARM: Implement the VFP versions of VMLA and VMLS.Gabe Black
2010-06-02ARM: Implement the VFP version of vdiv and vsqrt.Gabe Black
2010-06-02ARM: Implement the VFP version of vsub.Gabe Black
2010-06-02ARM: Implement the VFP version of vadd.Gabe Black
2010-06-02ARM: Implement the VFP version of vabs.Gabe Black
2010-06-02ARM: Implement the VFP version of vneg.Gabe Black
2010-06-02ARM: Implement the VFP version of vmul.Gabe Black
2010-06-02ARM: Move the VFP data operation decode into a function.Gabe Black
2010-06-02ARM: Decode ARM unconditional MRC and MCR instructions.Gabe Black
2010-06-02ARM: Move the CP15 decode block into a function.Gabe Black
2010-06-02ARM: Decode the unconditional version of ARM fp instructions.Gabe Black
2010-06-02ARM: Move the FP decode blocks into functions.Gabe Black
2010-06-02ARM: Warn/ignore when TLB maintenance operations are performed.Gabe Black
2010-06-02ARM: Convert the CP15 registers from MPU to MMU.Gabe Black
2010-06-02ARM: Decode the VSTR instruction.Gabe Black
2010-06-02ARM: BXJ should be BX when there is no J supportAli Saidi
2010-06-02ARM: Decode the VLDR instruction.Gabe Black
2010-06-02ARM: Decode all the various forms of vmov.Gabe Black
2010-06-02ARM: Decode the VMRS instruction.Gabe Black
2010-06-02ARM: Decode the VMSR instruction.Gabe Black
2010-06-02ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) regis...Gabe Black
2010-06-02ARM: Implement the udiv instruction.Gabe Black
2010-06-02ARM: Implement the sdiv instruction.Gabe Black
2010-06-02ARM: Decode the CPS instruction.Gabe Black
2010-06-02ARM: Decode the SRS instruction.Gabe Black
2010-06-02ARM: Decode TBB and TBH.Gabe Black
2010-06-02ARM: Decode the setend instruction.Gabe Black
2010-06-02ARM: Decode the arm version of ldrexd.Gabe Black
2010-06-02ARM: Decode the strex instructions.Gabe Black
2010-06-02ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.Gabe Black
2010-06-02ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.Gabe Black
2010-06-02ARM: Decode the RFE instruction.Gabe Black
2010-06-02ARM: Make sure some undefined thumb32 instructions fault.Gabe Black
2010-06-02ARM: Ignore/warn access to the bpimva registers.Gabe Black
2010-06-02ARM: Ignore/warn on accesses to the dccmvac register.Gabe Black
2010-06-02ARM: Decode the enterx and leavex instructions.Gabe Black
2010-06-02ARM: When an instruction is intentionally undefined, fault on it.Gabe Black