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2018-05-29arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOPGiacomo Travaglini
In the Arm ISA there are some sys reg numbers which are reserved for implementation defined registers. The default behaviour is to to treat them as unimplemented registers. It is now possible to change this behaviour at runtime and treat them as NOP. In this way an access to those register won't make simulation fail. Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10504 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-19arch-arm: Change disassemble when MSR to UNKNOWN registerGiacomo Travaglini
This patch changes the fault being thrown when MSR/MRS to an unknown Misc register in AArch64. While previously the instruction was decoded as an Unknown instruction (hence not printing any information), it is now decoded as a FailUnimplemented and the unrecognized System register numbers (CRn, op0...) are printed. Change-Id: I205ff7adcde5934231c77e8d2250db69a34581fc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10061 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-10arch-arm: Fix mrc,mcr to cop14 disassembleGiacomo Travaglini
This patch fixes the disassemble for AArch32 mcr/mrc p14 instructions. Change-Id: If5d7c2d7c726f040ae20053bf1d70f4405b34d0e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9681 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-03-26arch: Fix all override related warnings.Gabe Black
Clang has started(?) reporting override related warnings, something gcc apparently did before, but was disabled in the SConstruct. Rather than disable the warnings in for clang as well, this change fixes the warnings. A future change will re-enable the warnings for gcc. Change-Id: I3cc79e45749b2ae0f9bebb1acadc56a3d3a942da Reviewed-on: https://gem5-review.googlesource.com/9343 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-20arch, arm: Fix implicit-fallthrough GCC warningsChun-Chen Hsu
GCC 7 generates spurious fallthrough warnings in nested switch blocks where the inner switch block return. There is already a GCC fix [1] submitted for review but, until it is merged into GCC trunk, GEM5 will not build with GCC 7 due to these fallthrough warnings. This patch silences the spurious fallthrough warnings by appending a M5_UNREACHABLE statement in the outer switch cases. Note there is another GEM5 patch [2] to fix other fallthrough warnings. [1] https://gcc.gnu.org/ml/gcc-patches/2018-02/msg01105.html [2] https://gem5-review.googlesource.com/c/public/gem5/+/8541 Change-Id: I97cd8bfa90a88e93cee60cf27a8c93611d11a242 Signed-off-by: Chun-Chen Hsu <chunchenhsu@google.com> Reviewed-on: https://gem5-review.googlesource.com/9101 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-03-15arm: Fix implicit-fallthrough warnings when building with gcc-7+Siddhesh Poyarekar
gcc 7 onwards have additional heuristics to detect implicit fallthroughs and it fails the build with warnings for ARM as a result. There was one gcc bug[1] that I fixed but the rest are cases that gcc cannot detect due to the point at which it does the fallthrough check. Most of this patch adds __builtin_unreachable() hints in places that throw this warning to indicate to gcc that the fallthrough will never happen. The remaining cases are actually possible fallthroughs due to incorrect code running on the simulator; in which case an Unknown instruction is returned. [1] https://gcc.gnu.org/ml/gcc-patches/2018-02/msg01105.html Change-Id: I1baa9fa0ed15181c10c755c0bd777f88b607c158 Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/8541 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-02-20arch-arm: Add AArch32 HLT Semihosting interfaceGiacomo Travaglini
AArch32 HLT instruction is now able to issue Arm Semihosting commands as the AArch64 counterpart in either Arm and Thumb mode. Change-Id: I77da73d2e6a9288c704a5f646f4447022517ceb6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8372 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-20arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassemblyGiacomo Travaglini
This patch fixes the disassembly of AArch64 Exception Generating instructions, which were not printing the encoded immediate field. This has been accomplished by changing their underlying type to a newly defined one. Change-Id: If58ae3e620d2baa260e12ecdc850225adfcf1ee5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8368 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-19arch-arm: Add aarch64 semihosting supportAndreas Sandberg
Add basic support for Arm Semihosting 2.0 simulation calls [1]. These calls let the guest system call a simulator or debugger to request OS-like support when running bare metal code. With the exception of SYS_SYSTEM, this implementation supports all of the Semihosting 2.0 specification in aarch64. [1] https://developer.arm.com/docs/100863/latest/preface Change-Id: I08c153c18a4a4fb9f95d318e2a029724935192a7 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8147 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-02-16arch-arm: IMPLEMENTATION DEFINED registerGiacomo Travaglini
A new pseudo register has been added to the Misc pool. It is the implementation defined register. This kinds of registers are covered by the architecture and must be treated differently than UNIMPLEMENTED registers: their access can be trapped to EL2 (See HCR.TIDCP bit in the arm arm). Some previously undecoded registers in c9,c10,c11 have now this register type. Change-Id: Ibfc35982470b9dea0ecf39aaa6b1012a21852f53 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7922 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-16arch-arm: Decode Brk64 instructionsAndreas Sandberg
The brk instruction in aarch64 was decoded as an unimplemented instruction. Fix that. Change-Id: I3eb36a016ab56d882426c5cdef3a0b594de0f9cd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8142 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2017-12-05arm: Add support for the dc {civac, cvac, cvau, ivac} instrNikos Nikoleris
This patch adds support for decoding and executing the following ARMv8 cache maintenance instructions by Virtual Address: * dc civac: Clean and Invalidate by Virtual Address to the Point of Coherency * dc cvac: Clean by Virtual Address to the Point of Coherency * dc cvau: Clean by Virtual Address to the Point of Unification * dc ivac: Invalidate by Virtual Addrsess to the Point of Coherency Change-Id: I58cabda37f9636105fda1b1e84a0a04965fb5670 Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5060 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-12-05arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructionsNikos Nikoleris
This patch adds support for the ARMv7 cache maintenance intructions: * mcr dccmvac cleans a VA to the PoC * mcr dcimvac invalidates a VA to the PoC * mcr dccimvac cleans and invalidates a VA to the PoC * mcr dccmvau cleans a VA to the PoU Change-Id: I6511f203039ca145cc9128ddf61d09d6d7e40c10 Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5059 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-11-21arch-arm: Fix MSR/MRS disassembleGiacomo Travaglini
This patch is fixing the Aarch64 MSR/MRS disassemble, which was previously printing unexisting integer registers as source/destination operands rather than the system register name Change-Id: Iac9d5f2f2fea85abd9a398320ef7aa4844d43c0e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5861 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-15arm: Add support for armv8 CRC32 instructionsGiacomo Travaglini
This patch introduces the ARM A32/T32/A64 CRC Instructions, which are mandatory since ARMv8.1. The UNPREDICTABLE behaviours are implemented as follows: 1) CRC32(C)X (64 bit) instructions are decoded as Undefined in Aarch32 2) The instructions support predication in Aarch32 3) Using R15(PC) as source/dest operand is permitted in Aarch32 Change-Id: Iaf29b05874e1370c7615da79a07f111ded17b6cc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5521 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-13arch-arm: Corrected encoding for T32 HVC instructionGiacomo Travaglini
This patch corrects the encoding of the HVC (Hypervisor Call) for the T32 instruction set. Change-Id: I6f77eaf5c586697e9ccd588419c61e6d90c6c7bf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chuan Zhu <chuan.zhu@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5541 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-11-07alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates.Gabe Black
In the ISA instruction definitions, some classes were declared with execute, etc., functions outside of the main template because they had CPU specific signatures and would need to be duplicated with each CPU plugged into them. Now that the instructions always just use an ExecContext, there's no reason for those templates to be separate. This change folds those templates together. Change-Id: I13bda247d3d1cc07c0ea06968e48aa5b4aace7fa Reviewed-on: https://gem5-review.googlesource.com/5401 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-02alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.Gabe Black
The ISA parser used to generate different copies of exec functions for each exec context class a particular CPU wanted to use. That's since been changed so that those functions take a pointer to the base ExecContext, so the code which would generate those extra functions can be removed, and some functions which used to be templated on an ExecContext subclass can be untemplated, or minimally less templated. Now that some functions aren't going to be instantiated multiple times with different signatures, there are also opportunities to collapse templates and make many instruction definitions simpler within the parser. Since those changes will be less mechanical, they're left for later changes and will probably be done in smaller increments. Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea Reviewed-on: https://gem5-review.googlesource.com/5381 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-08-01arch-arm: Use named constants for m5op instructionsAndreas Sandberg
Change-Id: I544519c4f87e50cc02af29cbb3edc31ecf726e8e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4263 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2016-10-13isa,arm: Add missing AArch32 FP instructionsMitch Hayenga
This commit adds missing non-predicated, scalar floating point instructions. Specifically VRINT* floating point integer rounding instructions and VSEL* floating point conditional selects. Change-Id: I23cbd1389f151389ac8beb28a7d18d5f93d000e7 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
2016-09-15arm: Add m5_fail support for aarch64Ricardo Alves
Change-Id: Id2acbc09772be310a0eb9e33295afab07e08a4fa Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-02arm: Add AArch64 hypervisor call instruction 'hvc'Dylan Johnson
This patch adds the AArch64 instruction hvc which raises an exception from EL1 into EL2. The host OS uses this instruction to world switch into the guest. Change-Id: I930ee43f4f0abd4b35a68eb2a72e44e3ea6570be
2016-08-02arm: change instruction classes to catch hyp trapsDylan Johnson
Change-Id: I122918d0e3dfd01ae1a4ca4f19240a069115c8b7
2016-02-06style: remove trailing whitespaceSteve Reinhardt
Result of running 'hg m5style --skip-all --fix-white -a'.
2015-10-09isa: Add parameter to pick different decoder inside ISARekai Gonzalez Alberquilla
The decoder is responsible for splitting instructions in micro operations (uops). Given that different micro architectures may split operations differently, this patch allows to specify which micro architecture each isa implements, so different cores in the system can split instructions differently, also decoupling uop splitting (microArch) from ISA (Arch). This is done making the decodification calls templates that receive a type 'DecoderFlavour' that maps the name of the operation to the class that implements it. This way there is only one selection point (converting the command line enum to the appropriate DecodeFeatures object). In addition, there is no explicit code replication: template instantiation hides that, and the compiler should be able to resolve a number of things at compile-time.
2015-02-16arm: Merge ISA files with pseudo instructionsAndreas Sandberg
This changeset moves the pseudo instructions used to signal unknown instructions and unimplemented instructions to the same source files as the decoder fault.
2014-12-23arm: Raise an alignment fault if a PC has illegal alignmentAndreas Sandberg
We currently don't handle unaligned PCs correctly. There is one check for unaligned PCs in the TLB when running in aarch64 mode, but this check does not cover cases where the CPU does not do a TLB lookup when decoding an instruction (e.g., a branch stays within the same cache line). Additionally, the Decoder class sometimes throws an assertion for unaligned PCs which breaks speculation. This changeset introduces a decoder fault bit field in the ExtMachInst structure. This field can be used to signal a decoder failure. If set, the decoder generates an internal gem5fault instruction instead of a normal instruction. This instruction in turns either panics (fault type PANIC), returns an PCAlignmentFault (fault type UNALIGNED, aarch64) or PrefetchAbort (fault type UNALIGNED, aarch32). The patch causes minor changes to the realview64 regressions, and a stats bump will follow.
2014-10-29arm: Mark some miscregs (timer counter) registers at unverifiable.Ali Saidi
The checker can't verify timer registers, so it should just grab the version from the executing CPU, otherwise it could get a larger value and diverge execution.
2014-10-16arch: Use shared_ptr for all FaultsAndreas Hansson
This patch takes quite a large step in transitioning from the ad-hoc RefCountingPtr to the c++11 shared_ptr by adopting its use for all Faults. There are no changes in behaviour, and the code modifications are mostly just replacing "new" with "make_shared".
2014-10-01arm: More UBSan cleanups after additional full-system runsAndreas Hansson
Some incorrect casting to IntRegIndex, and a few uninitialized members in the i8254xGBe device.
2014-09-27arm: Fixed undefined behaviours identified by gccAndreas Hansson
This patch fixes the runtime errors highlighted by the undefined behaviour sanitizer. In the end there were two issues. First, when rotating an immediate, we ended up shifting an uint32_t by 32 in some cases. This case is fixed by checking for a rotation by 0 positions. Second, the Mrc15 and Mcr15 are operating on an IntReg and a MiscReg, but we used the type RegRegImmOp and passed a MiscRegIndex as an IntRegIndex. This issue is resolved by introducing a MiscRegRegImmOp and RegMiscRegImmOp with the appropriate types. With these fixes there are no runtime errors identified for the full ARM regressions.
2014-09-03arm: ISA X31 destination register fixAndrew Bardsley
This patch substituted the zero register for X31 used as a destination register. This prevents false dependencies based on X31.
2014-05-09arch: teach ISA parser how to split code across filesCurtis Dunham
This patch encompasses several interrelated and interdependent changes to the ISA generation step. The end goal is to reduce the size of the generated compilation units for instruction execution and decoding so that batch compilation can proceed with all CPUs active without exhausting physical memory. The ISA parser (src/arch/isa_parser.py) has been improved so that it can accept 'split [output_type];' directives at the top level of the grammar and 'split(output_type)' python calls within 'exec {{ ... }}' blocks. This has the effect of "splitting" the files into smaller compilation units. I use air-quotes around "splitting" because the files themselves are not split, but preprocessing directives are inserted to have the same effect. Architecturally, the ISA parser has had some changes in how it works. In general, it emits code sooner. It doesn't generate per-CPU files, and instead defers to the C preprocessor to create the duplicate copies for each CPU type. Likewise there are more files emitted and the C preprocessor does more substitution that used to be done by the ISA parser. Finally, the build system (SCons) needs to be able to cope with a dynamic list of source files coming out of the ISA parser. The changes to the SCons{cript,truct} files support this. In broad strokes, the targets requested on the command line are hidden from SCons until all the build dependencies are determined, otherwise it would try, realize it can't reach the goal, and terminate in failure. Since build steps (i.e. running the ISA parser) must be taken to determine the file list, several new build stages have been inserted at the very start of the build. First, the build dependencies from the ISA parser will be emitted to arch/$ISA/generated/inc.d, which is then read by a new SCons builder to finalize the dependencies. (Once inc.d exists, the ISA parser will not need to be run to complete this step.) Once the dependencies are known, the 'Environments' are made by the makeEnv() function. This function used to be called before the build began but now happens during the build. It is easy to see that this step is quite slow; this is a known issue and it's important to realize that it was already slow, but there was no obvious cause to attribute it to since nothing was displayed to the terminal. Since new steps that used to be performed serially are now in a potentially-parallel build phase, the pathname handling in the SCons scripts has been tightened up to deal with chdir() race conditions. In general, pathnames are computed earlier and more likely to be stored, passed around, and processed as absolute paths rather than relative paths. In the end, some of these issues had to be fixed by inserting serializing dependencies in the build. Minor note: For the null ISA, we just provide a dummy inc.d so SCons is never compelled to try to generate it. While it seems slightly wrong to have anything in src/arch/*/generated (i.e. a non-generated 'generated' file), it's by far the simplest solution.
2014-04-23arm: Don't use a stack allocated mnemonicMitchell Hayenga
FailUnimplemented passed a stack created mnemonic as a const char * which causes some grief when the stack goes away.
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
2013-05-14arm: Add support for the m5fail pseudo-opAndreas Sandberg
2013-02-19scons: Add warning for missing declarationsAndreas Hansson
This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code.
2013-02-19scons: Fix up numerous warnings about name shadowingAndreas Hansson
This patch address the most important name shadowing warnings (as produced when using gcc/clang with -Wshadow). There are many locations where constructor parameters and function parameters shadow local variables, but these are left unchanged.
2012-03-21ARM: Clean up condCodes in IT blocks.Ali Saidi
2012-03-01ARM: Add limited CP14 support.Matt Horsnell
New kernels attempt to read CP14 what debug architecture is available. These changes add the debug registers and return that none is currently available.
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31util: implements "writefile" gem5 op to export file from guest to host ↵Dam Sunwoo
filesystem Usage: m5 writefile <filename> File will be created in the gem5 output folder with the identical filename. Implementation is largely based on the existing "readfile" functionality. Currently does not support exporting of folders.
2012-01-07Merge with main repository.Gabe Black
2011-11-02SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.Gabe Black
2011-10-31GCC: Get everything working with gcc 4.6.1.Gabe Black
And by "everything" I mean all the quick regressions.
2011-09-13CP15 c15: enable execution with accesses to c15 registersChander Sudanthi
Previously, coprocessor accesses to CP15 c15 would fault. This patch enables accesses but prints out a warning, as the registers are not implemented.
2011-08-19ARM: Add support for DIV/SDIV instructions.Ali Saidi
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-05-13ARM: Construct the predicate test register for more instruction programatically.Ali Saidi
If one of the condition codes isn't being used in the execution we should only read it if the instruction might be dependent on it. With the preeceding changes there are several more cases where we should dynamically pick instead of assuming as we did before.
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions.
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