| Age | Commit message (Expand) | Author |
|---|
| 2019-05-17 | arch-arm: implement VMINNM and VMAXNM scalar version | Ciro Santilli |
| 2019-05-17 | arch-arm: implement VMINNM and VMAXNM SIMD version | Ciro Santilli |
| 2019-05-17 | arch-arm: rename operands to match spec in isa/formats/fp.isa | Ciro Santilli |
| 2019-05-11 | arch-arm: Add initial support for SVE contiguous loads/stores | Giacomo Gabrielli |
| 2019-03-25 | arch-arm: Add missing fall-through defaults | Javier Setoain |
| 2019-03-14 | arch-arm,cpu: Add initial support for Arm SVE | Giacomo Gabrielli |
| 2019-03-11 | arch-arm: Fixing implicit fallthrough build errors | Ryan Gambord |
| 2019-03-01 | arch-arm: implement floating point aarch32 VCVTA family | Ciro Santilli |
| 2019-01-23 | arch-arm: Implement LoadAcquire/StoreRelease in AArch32 | Giacomo Travaglini |
| 2019-01-23 | arch-arm: Remove SWP and SWPB instructions | Giacomo Travaglini |
| 2018-10-26 | arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL | Giacomo Travaglini |
| 2018-10-19 | arm: treat aarch64 hints as NOPs instead of panic | Ciro Santilli |
| 2018-10-19 | arm: update hint instruction decoding to match ARMv8.5 | Ciro Santilli |
| 2018-10-09 | arch-arm: AArch64 Crypto AES | Giacomo Travaglini |
| 2018-10-09 | arch-arm: AArch64 Crypto SHA | Giacomo Travaglini |
| 2018-10-09 | arch-arm: AArch32 Crypto AES | Matt Horsnell |
| 2018-10-09 | arch-arm: AArch32 Crypto SHA | Matt Horsnell |
| 2018-10-02 | arch-arm: Add FP16 support introduced by Armv8.2-A | Edmund Grimley Evans |
| 2018-08-10 | arm: Add support for RCpc load-acquire instructions (ARMv8.3) | Giacomo Gabrielli |
| 2018-06-22 | arch-arm: AArch32 execution triggering AArch64 SW Break | Giacomo Travaglini |
| 2018-06-22 | arch-arm: BadMode checking if corresponding EL is implemented | Giacomo Travaglini |
| 2018-06-14 | arch-arm: Add Illegal Execution flag to PCState | Giacomo Travaglini |
| 2018-05-29 | arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP | Giacomo Travaglini |
| 2018-04-19 | arch-arm: Change disassemble when MSR to UNKNOWN register | Giacomo Travaglini |
| 2018-04-10 | arch-arm: Fix mrc,mcr to cop14 disassemble | Giacomo Travaglini |
| 2018-03-26 | arch: Fix all override related warnings. | Gabe Black |
| 2018-03-20 | arch, arm: Fix implicit-fallthrough GCC warnings | Chun-Chen Hsu |
| 2018-03-15 | arm: Fix implicit-fallthrough warnings when building with gcc-7+ | Siddhesh Poyarekar |
| 2018-02-20 | arch-arm: Add AArch32 HLT Semihosting interface | Giacomo Travaglini |
| 2018-02-20 | arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassembly | Giacomo Travaglini |
| 2018-02-19 | arch-arm: Add aarch64 semihosting support | Andreas Sandberg |
| 2018-02-16 | arch-arm: IMPLEMENTATION DEFINED register | Giacomo Travaglini |
| 2018-02-16 | arch-arm: Decode Brk64 instructions | Andreas Sandberg |
| 2017-12-05 | arm: Add support for the dc {civac, cvac, cvau, ivac} instr | Nikos Nikoleris |
| 2017-12-05 | arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructions | Nikos Nikoleris |
| 2017-11-21 | arch-arm: Fix MSR/MRS disassemble | Giacomo Travaglini |
| 2017-11-15 | arm: Add support for armv8 CRC32 instructions | Giacomo Travaglini |
| 2017-11-13 | arch-arm: Corrected encoding for T32 HVC instruction | Giacomo Travaglini |
| 2017-11-07 | alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates. | Gabe Black |
| 2017-11-02 | alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts. | Gabe Black |
| 2017-08-01 | arch-arm: Use named constants for m5op instructions | Andreas Sandberg |
| 2016-10-13 | isa,arm: Add missing AArch32 FP instructions | Mitch Hayenga |
| 2016-09-15 | arm: Add m5_fail support for aarch64 | Ricardo Alves |
| 2016-08-02 | arm: Add AArch64 hypervisor call instruction 'hvc' | Dylan Johnson |
| 2016-08-02 | arm: change instruction classes to catch hyp traps | Dylan Johnson |
| 2016-02-06 | style: remove trailing whitespace | Steve Reinhardt |
| 2015-10-09 | isa: Add parameter to pick different decoder inside ISA | Rekai Gonzalez Alberquilla |
| 2015-02-16 | arm: Merge ISA files with pseudo instructions | Andreas Sandberg |
| 2014-12-23 | arm: Raise an alignment fault if a PC has illegal alignment | Andreas Sandberg |
| 2014-10-29 | arm: Mark some miscregs (timer counter) registers at unverifiable. | Ali Saidi |
