gem5 - gem5

Age	Commit message (Expand)	Author
2017-08-01	arch-arm: Use named constants for m5op instructions	Andreas Sandberg
2015-10-09	isa: Add parameter to pick different decoder inside ISA	Rekai Gonzalez Alberquilla
2014-12-23	arm: Raise an alignment fault if a PC has illegal alignment	Andreas Sandberg
2014-09-03	arch, cpu: Factor out the ExecContext into a proper base class	Andreas Sandberg
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2012-05-25	ISA: Make the decode function part of the ISA's decoder.	Gabe Black
2012-04-14	clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6	Andreas Hansson
2011-07-02	ISA: Use readBytes/writeBytes for all instruction level memory operations.	Gabe Black
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2010-11-08	ARM: Add support for M5 ops in the ARM ISA	Ali Saidi
2010-09-13	Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.	Gabe Black
2010-06-02	ARM: Implement the version of VMRS that writes to the APSR.	Gabe Black
2010-06-02	ARM: Introduce new VFP base classes that are optionally microops.	Gabe Black
2010-06-02	ARM: Add some support for wfi/wfe/yield/etc	Ali Saidi
2010-06-02	ARM: Define versions of MSR and MRS outside the decoder.	Gabe Black
2010-06-02	ARM: Remove unnecessary cruft from includes.isa.	Gabe Black
2010-06-02	ARM: Add base classes for multiply instructions.	Gabe Black
2009-07-01	ARM: Make DataOps select from a set of ways to set the c and v flags.	Gabe Black
2009-06-21	ARM: Simplify the ISA desc by pulling some classes out of it.	Gabe Black
2009-04-05	arm: add ARM support to M5	Stephen Hines