gem5 - gem5

Age	Commit message (Expand)	Author
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-08-25	ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing	Ali Saidi
2010-06-02	ARM: Decode to specialized conditional/unconditional versions of instructions.	Gabe Black
2010-06-02	ARM: Implement ARM CPU interrupts	Ali Saidi
2010-06-02	ARM: Implement the pkh instruction.	Gabe Black
2010-06-02	ARM: Implement the 8/16 bit signed/unsigned add/subtract half instructions.	Gabe Black
2010-06-02	ARM: Implement signed add/subtract and subtract/add.	Gabe Black
2010-06-02	ARM: Implement the unsigned 8 bit and 16 bit vector adds and subtracts.	Gabe Black
2010-06-02	ARM: Implement the unsigned saturating instructions.	Gabe Black
2010-06-02	ARM: Implement the ssub instructions.	Gabe Black
2010-06-02	ARM: Implement the SADD8 and SADD16 instructions.	Gabe Black
2010-06-02	ARM: Support instructions that set the GE bits when they write the condition ...	Gabe Black
2010-06-02	ARM: Implement signed saturating add and/or subtract instructions.	Gabe Black
2010-06-02	ARM: Add support for "SUBS PC, LR and related instructions".	Gabe Black
2010-06-02	ARM: Implement ADR as separate from ADD.	Gabe Black
2010-06-02	ARM: Add support for interworking branch ALU instructions.	Gabe Black
2010-06-02	ARM: Restrict the shift amount from a register to 8 bits.	Gabe Black
2010-06-02	ARM: Define a new "movt" data processing instruction.	Gabe Black
2010-06-02	ARM: Remove the special naming from the new version of data processing instru...	Gabe Black
2010-06-02	ARM: Implement data processing instructions external to the decoder.	Gabe Black