summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/insts/data.isa
AgeCommit message (Expand)Author
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2012-09-25ARM: Predict target of more instructions that modify PC.Ali Saidi
2012-06-29ARM: Fix identification of one RAS pop instruction.Ali Saidi
2011-09-26ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.Gabe Black
2011-05-13ARM: Generate condition code setting code based on which codes are set.Ali Saidi
2011-05-13ARM: Construct the predicate test register for more instruction programatically.Ali Saidi
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
2011-05-13ARM: Remove the saturating (Q) condition code from the renamed register.Ali Saidi
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
2011-05-04ARM: Implement WFE/WFI/SEV semantics.Prakash Ramrakhyani
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
2011-04-04ARM: Tag appropriate instructions as IsReturnAli Saidi
2011-01-18O3: Fix itstate prediction and recovery.Matt Horsnell
2010-12-09ARM: Take advantage of new PCState syntax.Gabe Black
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-08-25ARM: Make VMSR, RFE PC/LR etc non speculative, and serializingAli Saidi
2010-06-02ARM: Decode to specialized conditional/unconditional versions of instructions.Gabe Black
2010-06-02ARM: Implement ARM CPU interruptsAli Saidi
2010-06-02ARM: Implement the pkh instruction.Gabe Black
2010-06-02ARM: Implement the 8/16 bit signed/unsigned add/subtract half instructions.Gabe Black
2010-06-02ARM: Implement signed add/subtract and subtract/add.Gabe Black
2010-06-02ARM: Implement the unsigned 8 bit and 16 bit vector adds and subtracts.Gabe Black
2010-06-02ARM: Implement the unsigned saturating instructions.Gabe Black
2010-06-02ARM: Implement the ssub instructions.Gabe Black
2010-06-02ARM: Implement the SADD8 and SADD16 instructions.Gabe Black
2010-06-02ARM: Support instructions that set the GE bits when they write the condition ...Gabe Black
2010-06-02ARM: Implement signed saturating add and/or subtract instructions.Gabe Black
2010-06-02ARM: Add support for "SUBS PC, LR and related instructions".Gabe Black
2010-06-02ARM: Implement ADR as separate from ADD.Gabe Black
2010-06-02ARM: Add support for interworking branch ALU instructions.Gabe Black
2010-06-02ARM: Restrict the shift amount from a register to 8 bits.Gabe Black
2010-06-02ARM: Define a new "movt" data processing instruction.Gabe Black
2010-06-02ARM: Remove the special naming from the new version of data processing instru...Gabe Black
2010-06-02ARM: Implement data processing instructions external to the decoder.Gabe Black