gem5 - gem5

Age	Commit message (Expand)	Author
2019-08-12	arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func	Jordi Vaquero
2019-05-11	arch-arm: Add initial support for SVE contiguous loads/stores	Giacomo Gabrielli
2019-03-14	arch-arm,cpu: Add initial support for Arm SVE	Giacomo Gabrielli
2019-01-23	arch-arm: Remove SWP and SWPB instructions	Giacomo Travaglini
2018-10-09	arch-arm: AArch64 Crypto SHA	Giacomo Travaglini
2018-10-09	arch-arm: AArch32 Crypto SHA	Matt Horsnell
2014-05-09	arm: add preliminary ISA splits for ARM arch	Curtis Dunham
2014-05-09	arm: cleanup ARM ISA definition	Curtis Dunham
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2010-11-08	ARM: Add support for M5 ops in the ARM ISA	Ali Saidi
2010-08-25	ARM: Implement all ARM SIMD instructions.	Gabe Black
2010-06-02	ARM: Implement the VMSR instruction.	Gabe Black
2010-06-02	ARM: Implement the sdiv instruction.	Gabe Black
2010-06-02	ARM: Implement the swp and swpb instructions.	Gabe Black
2010-06-02	ARM: Implement SVC (was SWI) outside of the decoder.	Gabe Black
2010-06-02	ARM: Implement all integer multiply instructions.	Gabe Black
2010-06-02	ARM: Implement branch instructions external to the decoder.	Gabe Black
2010-06-02	ARM: Implement data processing instructions external to the decoder.	Gabe Black
2010-06-02	ARM: Reimplement load/store multiple external to the decoder.	Gabe Black
2010-06-02	ARM: Define the store instructions from outside the decoder.	Gabe Black
2010-06-02	ARM: Define the load instructions from outside the decoder.	Gabe Black