summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/insts/insts.isa
AgeCommit message (Collapse)Author
2019-01-23arch-arm: Remove SWP and SWPB instructionsGiacomo Travaglini
The SWP and SWPB instructions have been removed from AArch32. It was previously (ARMv7) possible to enable them with the ID_ISAR0.Swap bits, which are now hardcoded to 0b0000 (SWP and SWPB not implemented) Change-Id: Ic32b534454a7e0f7494a6f0b5e11182c65b3fe24 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15815 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-09arch-arm: AArch64 Crypto SHAGiacomo Travaglini
This patch implements the AArch64 secure hashing instructions from the Crypto extension. Change-Id: I2cdfa81b994637c880f2523fe37cdc6596d05cb1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13249 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-09arch-arm: AArch32 Crypto SHAMatt Horsnell
This patch implements the AArch32 secure hashing instructions from the Crypto extension. Change-Id: Iaba8424ab71800228a9aff039d93f5c35ee7d8e5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13247 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2014-05-09arm: add preliminary ISA splits for ARM archCurtis Dunham
2014-05-09arm: cleanup ARM ISA definitionCurtis Dunham
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
2010-11-08ARM: Add support for M5 ops in the ARM ISAAli Saidi
2010-08-25ARM: Implement all ARM SIMD instructions.Gabe Black
2010-06-02ARM: Implement the VMSR instruction.Gabe Black
2010-06-02ARM: Implement the sdiv instruction.Gabe Black
2010-06-02ARM: Implement the swp and swpb instructions.Gabe Black
2010-06-02ARM: Implement SVC (was SWI) outside of the decoder.Gabe Black
2010-06-02ARM: Implement all integer multiply instructions.Gabe Black
2010-06-02ARM: Implement branch instructions external to the decoder.Gabe Black
2010-06-02ARM: Implement data processing instructions external to the decoder.Gabe Black
2010-06-02ARM: Reimplement load/store multiple external to the decoder.Gabe Black
--HG-- rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/insts/macromem.isa rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/templates/macromem.isa
2010-06-02ARM: Define the store instructions from outside the decoder.Gabe Black
--HG-- rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa
2010-06-02ARM: Define the load instructions from outside the decoder.Gabe Black
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-20 19:35:06 +0000