gem5 - gem5

Age	Commit message (Expand)	Author
2010-11-08	ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.	Ali Saidi
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-08-25	ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing	Ali Saidi
2010-08-25	ARM: Use fewer micro-ops for register update loads if possible.	Gene WU
2010-08-25	ARM: Fix VFP enabled checks for mem instructions	Ali Saidi
2010-08-23	ARM: Exclusive accesses must be double word aligned	Ali Saidi
2010-08-23	ARM: Clean up the ISA desc portion of the ARM memory instructions.	Gabe Black
2010-06-02	ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.	Ali Saidi
2010-06-02	ARM: Implement ARM CPU interrupts	Ali Saidi
2010-06-02	ARM: Implement the VLDR instruction.	Gabe Black
2010-06-02	ARM: Implement the strex instructions.	Gabe Black
2010-06-02	ARM: Respect the E bit of the CPSR when doing loads and stores.	Gabe Black
2010-06-02	ARM: Implement the V7 version of alignment checking.	Gabe Black
2010-06-02	ARM: Implement the RFE instruction.	Gabe Black
2010-06-02	ARM: Explicitly keep track of the second destination for double loads/stores.	Gabe Black
2010-06-02	ARM: Implement the ldrex instruction.	Gabe Black
2010-06-02	ARM: Implemented prefetch instructions/decoding (pli, pld, pldw).	Gabe Black
2010-06-02	ARM: Make ldrs into the PC and ldm exception return do interworking branches.	Gabe Black
2010-06-02	ARM: Remove the special naming for the new memory instructions.	Gabe Black
2010-06-02	ARM: Pull double memory instructions out of the decoder.	Gabe Black
2010-06-02	ARM: Define the load instructions from outside the decoder.	Gabe Black