index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
arch
/
arm
/
isa
/
insts
/
ldr.isa
Age
Commit message (
Expand
)
Author
2010-08-25
ARM: Fix VFP enabled checks for mem instructions
Ali Saidi
2010-08-23
ARM: Exclusive accesses must be double word aligned
Ali Saidi
2010-08-23
ARM: Clean up the ISA desc portion of the ARM memory instructions.
Gabe Black
2010-06-02
ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.
Ali Saidi
2010-06-02
ARM: Implement ARM CPU interrupts
Ali Saidi
2010-06-02
ARM: Implement the VLDR instruction.
Gabe Black
2010-06-02
ARM: Implement the strex instructions.
Gabe Black
2010-06-02
ARM: Respect the E bit of the CPSR when doing loads and stores.
Gabe Black
2010-06-02
ARM: Implement the V7 version of alignment checking.
Gabe Black
2010-06-02
ARM: Implement the RFE instruction.
Gabe Black
2010-06-02
ARM: Explicitly keep track of the second destination for double loads/stores.
Gabe Black
2010-06-02
ARM: Implement the ldrex instruction.
Gabe Black
2010-06-02
ARM: Implemented prefetch instructions/decoding (pli, pld, pldw).
Gabe Black
2010-06-02
ARM: Make ldrs into the PC and ldm exception return do interworking branches.
Gabe Black
2010-06-02
ARM: Remove the special naming for the new memory instructions.
Gabe Black
2010-06-02
ARM: Pull double memory instructions out of the decoder.
Gabe Black
2010-06-02
ARM: Define the load instructions from outside the decoder.
Gabe Black