summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/insts/m5ops.isa
AgeCommit message (Expand)Author
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31util: implements "writefile" gem5 op to export file from guest to host filesy...Dam Sunwoo
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-16Merge yet again with the main repository.Gabe Black
2012-01-09ARM: Add support for initparam m5 opAli Saidi
2011-11-02SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.Gabe Black
2011-10-31GCC: Get everything working with gcc 4.6.1.Gabe Black
2011-09-18Pseudoinst: Add an initParam pseudo inst function.Gabe Black
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-04-04ARM: Fix m5op parameters bug.Ali Saidi
2011-03-17ARM: Allow conditional quiesce instructions.Ali Saidi
2010-11-08ARM: Add support for M5 ops in the ARM ISAAli Saidi