gem5 - gem5

Age	Commit message (Collapse)	Author
2016-09-15	arm: Add m5_fail support for aarch64	Ricardo Alves
	Change-Id: Id2acbc09772be310a0eb9e33295afab07e08a4fa Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-01-07	pseudo inst,util: Add optional key to initparam pseudo instruction	Gabor Dozsa
	The key parameter can be used to read out various config parameters from within the simulated software.
2014-03-23	arm: m5ops readfile64 args broken, offset coming through garbage	Eric Van Hensbergen
	There were several sections of the m5ops code which were essentially copy/pasted versions of the 32-bit code. The problem is that some of these didn't account fo4 64-bit registers leading to arguments being in the wrong registers. This patch addresses the args for readfile64, writefile64, and addsymbol64 -- all of which seemed to suffer from a similar set of problems when moving to 64-bit.
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
	Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
2013-05-14	arm: Add support for the m5fail pseudo-op	Andreas Sandberg

2013-02-19	scons: Add warning for missing declarations	Andreas Hansson
	This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code.
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black

2012-01-31	util: implements "writefile" gem5 op to export file from guest to host ↵	Dam Sunwoo
	filesystem Usage: m5 writefile <filename> File will be created in the gem5 output folder with the identical filename. Implementation is largely based on the existing "readfile" functionality. Currently does not support exporting of folders.
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
	Brings the CheckerCPU back to life to allow FS and SE checking of the O3CPU. These changes have only been tested with the ARM ISA. Other ISAs potentially require modification.
2012-01-16	Merge yet again with the main repository.	Gabe Black

2012-01-09	ARM: Add support for initparam m5 op	Ali Saidi

2011-11-02	SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.	Gabe Black

2011-10-31	GCC: Get everything working with gcc 4.6.1.	Gabe Black
	And by "everything" I mean all the quick regressions.
2011-09-18	Pseudoinst: Add an initParam pseudo inst function.	Gabe Black

2011-06-17	ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.	Gedare Bloom

2011-04-04	ARM: Fix m5op parameters bug.	Ali Saidi
	All the m5op parameters are 64 bits, but we were only sending 32 bits; and the static register indexes were incorrectly specified.
2011-03-17	ARM: Allow conditional quiesce instructions.	Ali Saidi
	This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage.
2010-11-08	ARM: Add support for M5 ops in the ARM ISA	Ali Saidi