gem5 - gem5

Age	Commit message (Expand)	Author
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2011-09-26	ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.	Gabe Black
2011-05-13	ARM: Construct the predicate test register for more instruction programatically.	Ali Saidi
2011-05-13	ARM: Further break up condition code into NZ, C, V bits.	Ali Saidi
2011-05-13	ARM: Break up condition codes into normal flags, saturation, and simd.	Ali Saidi
2011-04-04	ARM: Tag appropriate instructions as IsReturn	Ali Saidi
2011-03-17	ARM: Fix RFE macrop.	Matt Horsnell
2010-08-25	ARM: Use fewer micro-ops for register update loads if possible.	Gene WU
2010-08-23	ARM: Clean up the ISA desc portion of the ARM memory instructions.	Gabe Black
2010-06-02	ARM: Decode to specialized conditional/unconditional versions of instructions.	Gabe Black
2010-06-02	ARM: Implement the SRS instruction.	Gabe Black
2010-06-02	ARM: Implement the strex instructions.	Gabe Black
2010-06-02	ARM: Implement the V7 version of alignment checking.	Gabe Black
2010-06-02	ARM: Implement the RFE instruction.	Gabe Black
2010-06-02	ARM: Explicitly keep track of the second destination for double loads/stores.	Gabe Black
2010-06-02	ARM: Implement the swp and swpb instructions.	Gabe Black
2010-06-02	ARM: Move the templates for predicated instructions into a separate file.	Gabe Black
2010-06-02	ARM: Remove the special naming for the new memory instructions.	Gabe Black
2010-06-02	ARM: Define the load instructions from outside the decoder.	Gabe Black