index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
arch
/
arm
/
isa
/
insts
/
mult.isa
Age
Commit message (
Expand
)
Author
2011-09-26
ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.
Gabe Black
2011-05-13
ARM: Construct the predicate test register for more instruction programatically.
Ali Saidi
2011-05-13
ARM: Further break up condition code into NZ, C, V bits.
Ali Saidi
2011-05-13
ARM: Remove the saturating (Q) condition code from the renamed register.
Ali Saidi
2011-05-13
ARM: Break up condition codes into normal flags, saturation, and simd.
Ali Saidi
2011-04-04
ARM: Cleanup and small fixes to some NEON ops to match the spec.
William Wang
2010-11-15
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
Giacomo Gabrielli
2010-06-02
ARM: Decode to specialized conditional/unconditional versions of instructions.
Gabe Black
2010-06-02
ARM: Fix signed most significant multiply instructions.
Gabe Black
2010-06-02
ARM: Fix multiply overflow flag setting.
Gabe Black
2010-06-02
ARM: Fix multiply operations.
Gabe Black
2010-06-02
ARM: Remove special naming for the new version of multiply.
Gabe Black
2010-06-02
ARM: Implement all integer multiply instructions.
Gabe Black