| Age | Commit message (Expand) | Author |
|---|---|---|
| 2011-05-13 | ARM: Construct the predicate test register for more instruction programatically. | Ali Saidi |
| 2011-05-13 | ARM: Further break up condition code into NZ, C, V bits. | Ali Saidi |
| 2011-05-13 | ARM: Remove the saturating (Q) condition code from the renamed register. | Ali Saidi |
| 2011-05-13 | ARM: Break up condition codes into normal flags, saturation, and simd. | Ali Saidi |
| 2011-04-04 | ARM: Cleanup and small fixes to some NEON ops to match the spec. | William Wang |
| 2010-11-15 | CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. | Giacomo Gabrielli |
| 2010-06-02 | ARM: Decode to specialized conditional/unconditional versions of instructions. | Gabe Black |
| 2010-06-02 | ARM: Fix signed most significant multiply instructions. | Gabe Black |
| 2010-06-02 | ARM: Fix multiply overflow flag setting. | Gabe Black |
| 2010-06-02 | ARM: Fix multiply operations. | Gabe Black |
| 2010-06-02 | ARM: Remove special naming for the new version of multiply. | Gabe Black |
| 2010-06-02 | ARM: Implement all integer multiply instructions. | Gabe Black |
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