gem5 - gem5

Age	Commit message (Collapse)	Author
2011-09-26	ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.	Gabe Black
	By using an underscore, the "." is still available and can unambiguously be used to refer to members of a structure if an operand is a structure, class, etc. This change mostly just replaces the appropriate "."s with "_"s, but there were also a few places where the ISA descriptions where handling the extensions themselves and had their own regular expressions to update. The regular expressions in the isa parser were updated as well. It also now looks for one of the defined type extensions specifically after connecting "_" where before it would look for any sequence of characters after a "." following an operand name and try to use it as the extension. This helps to disambiguate cases where a "_" may legitimately be part of an operand name but not separate the name from the type suffix. Because leaving the "_" and suffix on the variable name still leaves a valid C++ identifier and all extensions need to be consistent in a given context, I considered leaving them on as a breadcrumb that would show what the intended type was for that operand. Unfortunately the operands can be referred to in code templates, the Mem operand in particular, and since the exact type of Mem can be different for different uses of the same template, that broke things.
2011-05-13	ARM: Construct the predicate test register for more instruction programatically.	Ali Saidi
	If one of the condition codes isn't being used in the execution we should only read it if the instruction might be dependent on it. With the preeceding changes there are several more cases where we should dynamically pick instead of assuming as we did before.
2011-05-13	ARM: Further break up condition code into NZ, C, V bits.	Ali Saidi
	Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions.
2011-05-13	ARM: Break up condition codes into normal flags, saturation, and simd.	Ali Saidi
	This change splits out the condcodes from being one monolithic register into three blocks that are updated independently. This allows CPUs to not have to do RMW operations on the flags registers for instructions that don't write all flags.
2011-03-17	ARM: Previous change didn't end up setting instFlags, this does.	Ali Saidi

2011-02-23	ARM: Mark store conditionals as such.	Matt Horsnell

2010-11-15	ARM: Fix SRS instruction to micro-code memory operation and register update.	Ali Saidi
	Previously the SRS instruction attempted to writeback in initiateAcc() which worked until a recent change, but was incorrect.
2010-08-25	ARM: Use fewer micro-ops for register update loads if possible.	Gene WU
	Allow some loads that update the base register to use just two micro-ops. three micro-ops are only used if the destination register matches the offset register or the PC is the destination regsiter. If the PC is updated it needs to be the last micro-op otherwise O3 will mispredict.
2010-08-25	ARM: Fix VFP enabled checks for mem instructions	Ali Saidi

2010-08-23	ARM: Exclusive accesses must be double word aligned	Ali Saidi

2010-08-23	ARM: Clean up the ISA desc portion of the ARM memory instructions.	Gabe Black

2010-06-02	ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.	Ali Saidi

2010-06-02	ARM: Implement the vstr instruction.	Gabe Black

2010-06-02	ARM: Implement the SRS instruction.	Gabe Black

2010-06-02	ARM: Implement the strex instructions.	Gabe Black

2010-06-02	ARM: Respect the E bit of the CPSR when doing loads and stores.	Gabe Black

2010-06-02	ARM: Implement the V7 version of alignment checking.	Gabe Black

2010-06-02	ARM: Explicitly keep track of the second destination for double loads/stores.	Gabe Black

2010-06-02	ARM: Remove the special naming for the new memory instructions.	Gabe Black
	These are the only memory instructions now.
2010-06-02	ARM: Pull double memory instructions out of the decoder.	Gabe Black

2010-06-02	ARM: Define the store instructions from outside the decoder.	Gabe Black
	--HG-- rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa