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path: root/src/arch/arm/isa/insts/str.isa
AgeCommit message (Expand)Author
2014-01-24arm: Add support for ARMv8 (AArch64 & AArch32)ARM gem5 Developers
2011-09-26ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.Gabe Black
2011-05-13ARM: Construct the predicate test register for more instruction programatically.Ali Saidi
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
2011-03-17ARM: Previous change didn't end up setting instFlags, this does.Ali Saidi
2011-02-23ARM: Mark store conditionals as such.Matt Horsnell
2010-11-15ARM: Fix SRS instruction to micro-code memory operation and register update.Ali Saidi
2010-08-25ARM: Use fewer micro-ops for register update loads if possible.Gene WU
2010-08-25ARM: Fix VFP enabled checks for mem instructionsAli Saidi
2010-08-23ARM: Exclusive accesses must be double word alignedAli Saidi
2010-08-23ARM: Clean up the ISA desc portion of the ARM memory instructions.Gabe Black
2010-06-02ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.Ali Saidi
2010-06-02ARM: Implement the vstr instruction.Gabe Black
2010-06-02ARM: Implement the SRS instruction.Gabe Black
2010-06-02ARM: Implement the strex instructions.Gabe Black
2010-06-02ARM: Respect the E bit of the CPSR when doing loads and stores.Gabe Black
2010-06-02ARM: Implement the V7 version of alignment checking.Gabe Black
2010-06-02ARM: Explicitly keep track of the second destination for double loads/stores.Gabe Black
2010-06-02ARM: Remove the special naming for the new memory instructions.Gabe Black
2010-06-02ARM: Pull double memory instructions out of the decoder.Gabe Black
2010-06-02ARM: Define the store instructions from outside the decoder.Gabe Black