gem5 - gem5

Age	Commit message (Expand)	Author
2011-01-18	ARM: Add support for moving predicated false dest operands from sources.	Ali Saidi
2010-12-09	ARM: Take advantage of new PCState syntax.	Gabe Black
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli
2010-12-07	O3: Support SWAP and predicated loads/store in ARM.	Min Kyu Jeong
2010-11-15	CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.	Giacomo Gabrielli
2010-11-15	ARM: Fix SRS instruction to micro-code memory operation and register update.	Ali Saidi
2010-11-08	ARM: Add support for M5 ops in the ARM ISA	Ali Saidi
2010-11-08	ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.	Ali Saidi
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-10-13	Mem: Change the CLREX flag to CLEAR_LL.	Gabe Black
2010-10-01	ARM: Clean up use of TBit and JBit.	Ali Saidi
2010-08-25	ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing	Ali Saidi
2010-08-25	ARM: Use fewer micro-ops for register update loads if possible.	Gene WU
2010-08-25	ARM: Fix VFP enabled checks for mem instructions	Ali Saidi
2010-08-25	ARM: Seperate out the renamable bits in the FPSCR.	Gabe Black
2010-08-25	ARM: Fix type comparison warnings in Neon.	Gabe Black
2010-08-25	ARM: Implement CPACR register and return Undefined Instruction when FP access...	Gabe Black
2010-08-25	ARM: Implement all ARM SIMD instructions.	Gabe Black
2010-08-23	ARM: Implement DBG instruction that doesn't do much for now.	Gene Wu
2010-08-23	MEM: Make CLREX a first class request operation and clear locks in caches whe...	Gene Wu
2010-08-23	ARM: Implement CLREX init/complete acc methods	Gene Wu
2010-08-23	ARM: Implement DSB, DMB, ISB	Gene Wu
2010-08-23	ARM: Implement CLREX	Gene Wu
2010-08-23	ARM: BX instruction can be contitional if last instruction in a IT block	Gene Wu
2010-08-23	ARM: mark msr/mrs instructions as SerializeBefore/After	Min Kyu Jeong
2010-08-23	ARM: Temporary local variables can't conflict with isa parser operands.	Gene Wu
2010-08-23	ARM: Exclusive accesses must be double word aligned	Ali Saidi
2010-08-23	ARM: Clean up the ISA desc portion of the ARM memory instructions.	Gabe Black
2010-06-02	ARM: Decode to specialized conditional/unconditional versions of instructions.	Gabe Black
2010-06-02	ARM: Implement a version of mcr and mrc that works in user mode.	Gabe Black
2010-06-02	ARM: Move some miscellaneous instructions out of the decoder to share with th...	Gabe Black
2010-06-02	ARM: Implement the bkpt instruction.	Gabe Black
2010-06-02	ARM: Make undefined instructions obey predication.	Gabe Black
2010-06-02	ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.	Gabe Black
2010-06-02	ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.	Ali Saidi
2010-06-02	ARM: Implement ARM CPU interrupts	Ali Saidi
2010-06-02	ARM: Implement conversion to/from half precision.	Gabe Black
2010-06-02	ARM: Clean up VFP	Gabe Black
2010-06-02	ARM: Clean up the implementation of the VFP instructions.	Gabe Black
2010-06-02	ARM: Implement the version of VMRS that writes to the APSR.	Gabe Black
2010-06-02	ARM: Implement the VCMPE instruction.	Gabe Black
2010-06-02	ARM: Fix vcvtr so that it uses the rounding mode in the FPSCR.	Gabe Black
2010-06-02	ARM: Fix saturation of VCVT from fp to integer.	Gabe Black
2010-06-02	ARM: Compensate for ARM's underflow coming from -before- rounding, but x86's ...	Gabe Black
2010-06-02	ARM: Implement flush to zero for destinations as well.	Gabe Black
2010-06-02	ARM: Fix up nans to match ARM's expected behavior.	Gabe Black
2010-06-02	ARM: Implement flush to zero mode for VFP, and clean up some corner cases.	Gabe Black
2010-06-02	ARM: Add barriers that make sure FP operations happen where they're supposed to.	Gabe Black
2010-06-02	ARM: Implement the version of VCVT float to int that rounds towards zero.	Gabe Black
2010-06-02	ARM: Implement the floating/fixed point VCVT instructions.	Gabe Black