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path: root/src/arch/arm/isa/insts
AgeCommit message (Expand)Author
2012-01-09ARM: Add support for initparam m5 opAli Saidi
2011-12-01ARM: Add IsSerializeAfter and IsNonSpeculative flag to the syscall instruction .Ali Saidi
2011-10-31GCC: Get everything working with gcc 4.6.1.Gabe Black
2011-09-26ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.Gabe Black
2011-09-18Pseudoinst: Add an initParam pseudo inst function.Gabe Black
2011-08-19Fix bugs due to interaction between SEV instructions and O3 pipelineGeoffrey Blake
2011-07-15ARM: Fix SWP/SWPB undefined instruction behaviorWade Walker
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-05-18gcc: fix an uninitialized variable warning from G++ 4.5Nathan Binkert
2011-05-13ARM: Generate condition code setting code based on which codes are set.Ali Saidi
2011-05-13ARM: Construct the predicate test register for more instruction programatically.Ali Saidi
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
2011-05-13ARM: Remove the saturating (Q) condition code from the renamed register.Ali Saidi
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
2011-05-04ARM: Implement WFE/WFI/SEV semantics.Prakash Ramrakhyani
2011-04-04ARM: Use CPU local lock before sending load to mem system.Ali Saidi
2011-04-04ARM: Cleanup and small fixes to some NEON ops to match the spec.William Wang
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
2011-04-04ARM: Fix m5op parameters bug.Ali Saidi
2011-04-04ARM: Tag appropriate instructions as IsReturnAli Saidi
2011-03-17ARM: Fix subtle bug in LDM.Ali Saidi
2011-03-17ARM: Identify branches as conditional or unconditional and direct or indirect.Ali Saidi
2011-03-17ARM: Allow conditional quiesce instructions.Ali Saidi
2011-03-17ARM: Fix RFE macrop.Matt Horsnell
2011-03-17ARM: Rename registers used as temporary state by microops.Matt Horsnell
2011-03-17ARM: Previous change didn't end up setting instFlags, this does.Ali Saidi
2011-02-23ARM: Squash state on FPSCR stride or len write.Ali Saidi
2011-02-23ARM: Mark store conditionals as such.Matt Horsnell
2011-02-23ARM: Do something for ISB, DSB, DMBAli Saidi
2011-02-23ARM: Make Noop actually decode to a noop and set it's instflags.Ali Saidi
2011-01-18O3: Fix itstate prediction and recovery.Matt Horsnell
2011-01-18ARM: The ARM decoder should not panic when decoding undefined holes is arch.Matt Horsnell
2011-01-18ARM: Add support for moving predicated false dest operands from sources.Ali Saidi
2010-12-09ARM: Take advantage of new PCState syntax.Gabe Black
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-12-07O3: Support SWAP and predicated loads/store in ARM.Min Kyu Jeong
2010-11-15CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.Giacomo Gabrielli
2010-11-15ARM: Fix SRS instruction to micro-code memory operation and register update.Ali Saidi
2010-11-08ARM: Add support for M5 ops in the ARM ISAAli Saidi
2010-11-08ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.Ali Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-10-13Mem: Change the CLREX flag to CLEAR_LL.Gabe Black
2010-10-01ARM: Clean up use of TBit and JBit.Ali Saidi
2010-08-25ARM: Make VMSR, RFE PC/LR etc non speculative, and serializingAli Saidi
2010-08-25ARM: Use fewer micro-ops for register update loads if possible.Gene WU
2010-08-25ARM: Fix VFP enabled checks for mem instructionsAli Saidi
2010-08-25ARM: Seperate out the renamable bits in the FPSCR.Gabe Black
2010-08-25ARM: Fix type comparison warnings in Neon.Gabe Black
2010-08-25ARM: Implement CPACR register and return Undefined Instruction when FP access...Gabe Black
2010-08-25ARM: Implement all ARM SIMD instructions.Gabe Black