gem5 - gem5

Age	Commit message (Expand)	Author
2016-10-15	cpu, arm: Distinguish Float* and SimdFloat, create FloatMem opClass	Fernando Endo
2016-10-13	isa,arm: Add missing AArch32 FP instructions	Mitch Hayenga
2016-09-15	arm: Add m5_fail support for aarch64	Ricardo Alves
2016-08-02	arm: Fix trapping to Hypervisor during MSR/MRS read/write	Dylan Johnson
2016-08-02	arm: Add AArch64 hypervisor call instruction 'hvc'	Dylan Johnson
2016-06-02	arm: Rewrite ERET to behave according to the ARMv8 ARM	Andreas Sandberg
2016-06-02	arm: Correctly check FP/SIMD access permission in aarch32	Andreas Sandberg
2016-04-13	misc: Fix issues flagged by gcc 6	Andreas Hansson
2016-02-29	arm: Squash after returning from exceptions in v7	Mitch Hayenga
2016-01-07	pseudo inst,util: Add optional key to initparam pseudo instruction	Gabor Dozsa
2015-10-09	isa: Add parameter to pick different decoder inside ISA	Rekai Gonzalez Alberquilla
2015-09-30	isa,cpu: Add support for FS SMT Interrupts	Mitch Hayenga
2015-06-09	arm: Fix typo in ldrsh instruction name	Rune Holm
2015-05-05	arm: Add missing FPEXC.EN check	Andreas Hansson
2014-11-14	arm: Fixes based on UBSan and static analysis	Andreas Hansson
2014-09-02	arm: Don't speculatively access most miscregisters.	Akash Bagdia
2014-10-16	arch: Use shared_ptr for all Faults	Andreas Hansson
2014-09-27	arm: Fixed undefined behaviours identified by gcc	Andreas Hansson
2014-09-03	arm: Make memory ops work on 64bit/128-bit quantities	Mitch Hayenga
2014-09-03	arm: Fix v8 neon latency issue for loads/stores	Mitch Hayenga
2014-09-03	arm: Mark v7 cbz instructions as direct branches	Mitch Hayenga
2014-04-17	arm: Make sure UndefinedInstructions are properly initialized	Ali Saidi
2014-05-09	arm: add preliminary ISA splits for ARM arch	Curtis Dunham
2014-05-09	arm: Panics in miscreg read functions can be tripped by O3 model	Geoffrey Blake
2014-05-09	arm: cleanup ARM ISA definition	Curtis Dunham
2014-03-23	arm: m5ops readfile64 args broken, offset coming through garbage	Eric Van Hensbergen
2014-01-24	arm: Add support for ARMv8 (AArch64 & AArch32)	ARM gem5 Developers
2013-05-14	arm: Add support for the m5fail pseudo-op	Andreas Sandberg
2013-02-19	scons: Fix warnings issued by clang 3.2svn (XCode 4.6)	Andreas Hansson
2013-02-19	scons: Add warning for missing declarations	Andreas Hansson
2013-02-15	arm: fix some fp comparisons that worked by accident.	Ali Saidi
2012-09-25	ARM: Predict target of more instructions that modify PC.	Ali Saidi
2012-06-29	ARM: Fix identification of one RAS pop instruction.	Ali Saidi
2012-03-21	ARM: IT doesn't need to be serializing.	Geoffrey Blake
2012-03-01	ARM: Add limited CP14 support.	Matt Horsnell
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	util: implements "writefile" gem5 op to export file from guest to host filesy...	Dam Sunwoo
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-16	Merge yet again with the main repository.	Gabe Black
2012-01-09	ARM: Add support for initparam m5 op	Ali Saidi
2012-01-07	Merge with the main repository again.	Gabe Black
2012-01-07	Merge with main repository.	Gabe Black
2011-12-01	ARM: Add IsSerializeAfter and IsNonSpeculative flag to the syscall instruction .	Ali Saidi
2011-11-02	SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.	Gabe Black
2011-10-31	GCC: Get everything working with gcc 4.6.1.	Gabe Black
2011-09-26	ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.	Gabe Black
2011-09-18	Pseudoinst: Add an initParam pseudo inst function.	Gabe Black
2011-08-19	Fix bugs due to interaction between SEV instructions and O3 pipeline	Geoffrey Blake
2011-07-15	ARM: Fix SWP/SWPB undefined instruction behavior	Wade Walker
2011-06-17	ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.	Gedare Bloom