gem5 - gem5

Age	Commit message (Expand)	Author
2013-05-14	arm: Add support for the m5fail pseudo-op	Andreas Sandberg
2013-02-19	scons: Fix warnings issued by clang 3.2svn (XCode 4.6)	Andreas Hansson
2013-02-19	scons: Add warning for missing declarations	Andreas Hansson
2013-02-15	arm: fix some fp comparisons that worked by accident.	Ali Saidi
2012-09-25	ARM: Predict target of more instructions that modify PC.	Ali Saidi
2012-06-29	ARM: Fix identification of one RAS pop instruction.	Ali Saidi
2012-03-21	ARM: IT doesn't need to be serializing.	Geoffrey Blake
2012-03-01	ARM: Add limited CP14 support.	Matt Horsnell
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	util: implements "writefile" gem5 op to export file from guest to host filesy...	Dam Sunwoo
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-16	Merge yet again with the main repository.	Gabe Black
2012-01-09	ARM: Add support for initparam m5 op	Ali Saidi
2012-01-07	Merge with the main repository again.	Gabe Black
2012-01-07	Merge with main repository.	Gabe Black
2011-12-01	ARM: Add IsSerializeAfter and IsNonSpeculative flag to the syscall instruction .	Ali Saidi
2011-11-02	SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.	Gabe Black
2011-10-31	GCC: Get everything working with gcc 4.6.1.	Gabe Black
2011-09-26	ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.	Gabe Black
2011-09-18	Pseudoinst: Add an initParam pseudo inst function.	Gabe Black
2011-08-19	Fix bugs due to interaction between SEV instructions and O3 pipeline	Geoffrey Blake
2011-07-15	ARM: Fix SWP/SWPB undefined instruction behavior	Wade Walker
2011-06-17	ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.	Gedare Bloom
2011-05-18	gcc: fix an uninitialized variable warning from G++ 4.5	Nathan Binkert
2011-05-13	ARM: Generate condition code setting code based on which codes are set.	Ali Saidi
2011-05-13	ARM: Construct the predicate test register for more instruction programatically.	Ali Saidi
2011-05-13	ARM: Further break up condition code into NZ, C, V bits.	Ali Saidi
2011-05-13	ARM: Remove the saturating (Q) condition code from the renamed register.	Ali Saidi
2011-05-13	ARM: Break up condition codes into normal flags, saturation, and simd.	Ali Saidi
2011-05-04	ARM: Implement WFE/WFI/SEV semantics.	Prakash Ramrakhyani
2011-04-04	ARM: Use CPU local lock before sending load to mem system.	Ali Saidi
2011-04-04	ARM: Cleanup and small fixes to some NEON ops to match the spec.	William Wang
2011-04-04	ARM: Cleanup implementation of ITSTATE and put important code in PCState.	Ali Saidi
2011-04-04	ARM: Fix m5op parameters bug.	Ali Saidi
2011-04-04	ARM: Tag appropriate instructions as IsReturn	Ali Saidi
2011-03-17	ARM: Fix subtle bug in LDM.	Ali Saidi
2011-03-17	ARM: Identify branches as conditional or unconditional and direct or indirect.	Ali Saidi
2011-03-17	ARM: Allow conditional quiesce instructions.	Ali Saidi
2011-03-17	ARM: Fix RFE macrop.	Matt Horsnell
2011-03-17	ARM: Rename registers used as temporary state by microops.	Matt Horsnell
2011-03-17	ARM: Previous change didn't end up setting instFlags, this does.	Ali Saidi
2011-02-23	ARM: Squash state on FPSCR stride or len write.	Ali Saidi
2011-02-23	ARM: Mark store conditionals as such.	Matt Horsnell
2011-02-23	ARM: Do something for ISB, DSB, DMB	Ali Saidi
2011-02-23	ARM: Make Noop actually decode to a noop and set it's instflags.	Ali Saidi
2011-01-18	O3: Fix itstate prediction and recovery.	Matt Horsnell
2011-01-18	ARM: The ARM decoder should not panic when decoding undefined holes is arch.	Matt Horsnell
2011-01-18	ARM: Add support for moving predicated false dest operands from sources.	Ali Saidi
2010-12-09	ARM: Take advantage of new PCState syntax.	Gabe Black
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli