gem5 - gem5

Age	Commit message (Expand)	Author
2011-04-04	ARM: Use CPU local lock before sending load to mem system.	Ali Saidi
2011-04-04	ARM: Cleanup and small fixes to some NEON ops to match the spec.	William Wang
2011-04-04	ARM: Cleanup implementation of ITSTATE and put important code in PCState.	Ali Saidi
2011-04-04	ARM: Fix m5op parameters bug.	Ali Saidi
2011-04-04	ARM: Tag appropriate instructions as IsReturn	Ali Saidi
2011-03-17	ARM: Fix subtle bug in LDM.	Ali Saidi
2011-03-17	ARM: Identify branches as conditional or unconditional and direct or indirect.	Ali Saidi
2011-03-17	ARM: Allow conditional quiesce instructions.	Ali Saidi
2011-03-17	ARM: Fix RFE macrop.	Matt Horsnell
2011-03-17	ARM: Rename registers used as temporary state by microops.	Matt Horsnell
2011-03-17	ARM: Previous change didn't end up setting instFlags, this does.	Ali Saidi
2011-02-23	ARM: Squash state on FPSCR stride or len write.	Ali Saidi
2011-02-23	ARM: Mark store conditionals as such.	Matt Horsnell
2011-02-23	ARM: Do something for ISB, DSB, DMB	Ali Saidi
2011-02-23	ARM: Make Noop actually decode to a noop and set it's instflags.	Ali Saidi
2011-01-18	O3: Fix itstate prediction and recovery.	Matt Horsnell
2011-01-18	ARM: The ARM decoder should not panic when decoding undefined holes is arch.	Matt Horsnell
2011-01-18	ARM: Add support for moving predicated false dest operands from sources.	Ali Saidi
2010-12-09	ARM: Take advantage of new PCState syntax.	Gabe Black
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli
2010-12-07	O3: Support SWAP and predicated loads/store in ARM.	Min Kyu Jeong
2010-11-15	CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.	Giacomo Gabrielli
2010-11-15	ARM: Fix SRS instruction to micro-code memory operation and register update.	Ali Saidi
2010-11-08	ARM: Add support for M5 ops in the ARM ISA	Ali Saidi
2010-11-08	ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.	Ali Saidi
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-10-13	Mem: Change the CLREX flag to CLEAR_LL.	Gabe Black
2010-10-01	ARM: Clean up use of TBit and JBit.	Ali Saidi
2010-08-25	ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing	Ali Saidi
2010-08-25	ARM: Use fewer micro-ops for register update loads if possible.	Gene WU
2010-08-25	ARM: Fix VFP enabled checks for mem instructions	Ali Saidi
2010-08-25	ARM: Seperate out the renamable bits in the FPSCR.	Gabe Black
2010-08-25	ARM: Fix type comparison warnings in Neon.	Gabe Black
2010-08-25	ARM: Implement CPACR register and return Undefined Instruction when FP access...	Gabe Black
2010-08-25	ARM: Implement all ARM SIMD instructions.	Gabe Black
2010-08-23	ARM: Implement DBG instruction that doesn't do much for now.	Gene Wu
2010-08-23	MEM: Make CLREX a first class request operation and clear locks in caches whe...	Gene Wu
2010-08-23	ARM: Implement CLREX init/complete acc methods	Gene Wu
2010-08-23	ARM: Implement DSB, DMB, ISB	Gene Wu
2010-08-23	ARM: Implement CLREX	Gene Wu
2010-08-23	ARM: BX instruction can be contitional if last instruction in a IT block	Gene Wu
2010-08-23	ARM: mark msr/mrs instructions as SerializeBefore/After	Min Kyu Jeong
2010-08-23	ARM: Temporary local variables can't conflict with isa parser operands.	Gene Wu
2010-08-23	ARM: Exclusive accesses must be double word aligned	Ali Saidi
2010-08-23	ARM: Clean up the ISA desc portion of the ARM memory instructions.	Gabe Black
2010-06-02	ARM: Decode to specialized conditional/unconditional versions of instructions.	Gabe Black
2010-06-02	ARM: Implement a version of mcr and mrc that works in user mode.	Gabe Black
2010-06-02	ARM: Move some miscellaneous instructions out of the decoder to share with th...	Gabe Black
2010-06-02	ARM: Implement the bkpt instruction.	Gabe Black
2010-06-02	ARM: Make undefined instructions obey predication.	Gabe Black