gem5 - gem5

Age	Commit message (Expand)	Author
2011-04-04	ARM: Use CPU local lock before sending load to mem system.	Ali Saidi
2011-04-04	ARM: Cleanup implementation of ITSTATE and put important code in PCState.	Ali Saidi
2011-04-04	ARM: Fix m5op parameters bug.	Ali Saidi
2011-03-17	ARM: Rename registers used as temporary state by microops.	Matt Horsnell
2011-01-18	O3: Fix itstate prediction and recovery.	Matt Horsnell
2010-12-09	ARM: Take advantage of new PCState syntax.	Gabe Black
2010-12-09	ARM: Get rid of some unused FP operands.	Gabe Black
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli
2010-11-08	ARM: Add support for M5 ops in the ARM ISA	Ali Saidi
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-08-25	ARM: Seperate out the renamable bits in the FPSCR.	Gabe Black
2010-08-25	ARM: Implement CPACR register and return Undefined Instruction when FP access...	Gabe Black
2010-08-25	ARM: Implement all ARM SIMD instructions.	Gabe Black
2010-06-02	ARM: Decode to specialized conditional/unconditional versions of instructions.	Gabe Black
2010-06-02	ARM: Implement the bkpt instruction.	Gabe Black
2010-06-02	ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.	Gabe Black
2010-06-02	ARM: Make integer division by zero return a fault.	Gabe Black
2010-06-02	ARM: Add some support for wfi/wfe/yield/etc	Ali Saidi
2010-06-02	ARM: Add fp operands to operands.isa.	Gabe Black
2010-06-02	ARM: Allow flattening into any mode.	Gabe Black
2010-06-02	ARM: Implement the strex instructions.	Gabe Black
2010-06-02	ARM: Squash the low order bits of the PC when performing a regular branch.	Gabe Black
2010-06-02	ARM: When changing the CPSR and branching, make sure the branch is second.	Gabe Black
2010-06-02	ARM: Explicitly keep track of the second destination for double loads/stores.	Gabe Black
2010-06-02	ARM: Add a version of the Dest and Op1 operands for accessing the MiscRegs.	Gabe Black
2010-06-02	ARM: Add a base class to support usada8.	Gabe Black
2010-06-02	ARM: Make LDM that loads the PC perform an interworking branch.	Gabe Black
2010-06-02	ARM: Align the PC when using it as the base for a load.	Gabe Black
2010-06-02	ARM: Add support for interworking branch ALU instructions.	Gabe Black
2010-06-02	ARM: Add an fp version of one of the microop indexed registers.	Gabe Black
2010-06-02	ARM: Eliminate the unused rhi and rlo operands.	Gabe Black
2010-06-02	ARM: Implement all integer multiply instructions.	Gabe Black
2010-06-02	ARM: Implement branch instructions external to the decoder.	Gabe Black
2010-06-02	ARM: Replace the interworking branch base class with a special operand.	Gabe Black
2010-06-02	ARM: Fix PC operand handling.	Gabe Black
2010-06-02	ARM: Add new base classes for data processing instructions.	Gabe Black
2010-06-02	ARM: Define the load instructions from outside the decoder.	Gabe Black
2010-06-02	ARM: Add an operand for accessing the current PC.	Gabe Black
2010-06-02	ARM: Track the current ISA mode using the PC.	Gabe Black
2010-06-02	ARM: Remove IsControl from operands that don't imply control transfers.	Gabe Black
2009-11-14	ARM: More accurately describe the effects of using the control operands.	Gabe Black
2009-11-14	ARM: Hook up the moded versions of the SPSR.	Gabe Black
2009-11-10	ARM: Fix some bugs in the ISA desc and fill out some instructions.	Gabe Black
2009-11-08	ARM: Split the condition codes out of the CPSR.	Gabe Black
2009-11-08	ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.	Gabe Black
2009-11-08	ARM: Get rid of the Raddr operand.	Gabe Black
2009-07-27	ARM: Add in spots for the VFP control registers.	Gabe Black
2009-07-27	ARM: Handle register indexed system calls.	Ali Saidi
2009-07-08	ARM: Use custom read/write code to alias R15 with the PC.	Gabe Black
2009-07-08	ARM: Move the integer microops out of the decoder and into the ISA desc.	Gabe Black